MOSFET Gate Electrode Layout for Leakage-Safe Scaling
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Solution Overview
Problem
The scaling down of metal oxide semiconductor field effect transistors (MOSFETs) is hindered by increased leakage current at the connection portions of gate electrodes due to thinner interlayer insulating layers, which complicates the miniaturization process.
Innovation Solution
A semiconductor device design incorporating a silicon carbide layer with specific conductive type regions and strategically arranged gate electrodes, where the distances between gate electrodes satisfy certain expressions to optimize the interlayer insulating layer thickness and prevent short circuits, thereby enhancing the scalability and reliability of the MOSFET.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the MOSFET is scaled down, then the device size is reduced, but the interlayer insulating layer becomes thinner and leakage current increases
Solution Approach 1:
The patent applies local quality by creating an asymmetric gate electrode arrangement where the first distance (between first and second gate electrodes) is set to be larger than the second distance (between second and third gate electrodes). This local structural variation optimizes the interlayer insulating layer thickness distribution, ensuring sufficient insulation where needed while enabling overall device scaling down.
2Productivity
If the interlayer insulating layer is made thinner to reduce device size, then the device can be scaled down, but leakage current at connection portions increases
Solution Approach 1:
The patent employs parameter changes by specifically controlling the relationship between the first distance and second distance of gate electrodes. By setting the first distance to be larger than the second distance, the patent optimizes the interlayer insulating layer thickness parameter, allowing the layer to be sufficiently thin for scaling while preventing excessive leakage current through the asymmetric configuration.
Data Source
AI summary
A semiconductor device of embodiments includes a first gate electrode, a second gate electrode, a third gate electrode extending in a first direction, and a gate wiring line extending in a second direction crossing the first direction and to which the first to the third gate electrodes are connected. Assuming distance between the first and the second gate electrode in the second direction in a first region is S1, distance between the first and the second gate electrode in the second direction in a second region closer to the gate wiring line than the first region is S2, distance between the second and the third gate electrode in the second direction in the first region is S3, and distance between the second and the third gate electrode in the second direction in the second region is S4, following Expressions are satisfied,S1<S3, S1<S2, S3>S4.