Vertical MOSFET Gate Length Control via Layer Segmentation
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Solution Overview
Problem
The miniaturization trend in vertical MOSFETs has led to non-uniformity in gate length, causing instability in device characteristics, making it difficult to maintain consistent performance.
Innovation Solution
A semiconductor device structure is developed with a specific arrangement of semiconductor layers and impurity concentrations, where a p− type well and frame area are created using ion implantation to define a precise gate length, and a gate insulator and electrode are positioned to enhance control over the gate length, allowing for stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical MOSFETs are miniaturized to increase channel density, then productivity and device capacity are improved, but manufacturing precision deteriorates due to non-uniform gate length
Solution Approach 1:
The device is divided into multiple semiconductor layers (first, second, and third semiconductor layers) with different conductive types and impurity concentrations. The gate structure is segmented into a gate insulator and gate electrode positioned on specific layers. This segmentation allows independent optimization of each layer's properties to maintain gate length uniformity while achieving miniaturization and increased channel density.
Solution Approach 2:
Different regions of the device are assigned different impurity concentrations and conductive types. The first semiconductor layer has a first impurity concentration, the second layer has a second impurity concentration, and the third layer has a third impurity concentration. This local differentiation enables precise control of electrical properties in each region, ensuring uniform gate length characteristics even as the overall device is miniaturized to increase channel density.
2Productivity
If gate length is reduced to increase channel density, then productivity is improved, but device characteristics become unstable
Solution Approach 1:
The gate insulator and gate electrode are positioned on the second semiconductor layer before final device assembly, establishing a stable reference plane for gate length definition. The impurity concentrations in the three semiconductor layers are predetermined and controlled to ensure uniform electrical characteristics. This preliminary structuring prevents characteristic instability that would otherwise occur with reduced gate length.
Solution Approach 2:
The invention controls multiple parameters simultaneously: impurity concentrations in three different semiconductor layers, the positioning of the gate insulator and gate electrode, and the relative arrangements of the semiconductor layers. By carefully adjusting these parameters, the device achieves miniaturization with stable characteristics, as the combined effect of these parameter controls compensates for the reduced gate length.
3Productivity
If miniaturization is pursued to increase channel density, then productivity is improved, but manufacturing precision deteriorates
Solution Approach 1:
The invention transitions from controlling gate length in a single dimension to controlling it through multiple dimensional parameters: the thickness and positioning of three different semiconductor layers, the location of the gate insulator, and the gate electrode position. This multi-dimensional approach provides additional degrees of freedom for precision control, enabling accurate gate length definition even as the overall device size is reduced to increase channel density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control over the gate length, reducing variations in device characteristics and preventing issues like increased leakage current or on-resistance, while allowing for a finer unit cell design and increased channel density.
Implementation Method 1
implanting impurities having the second conductive type in a periphery portion of an area on the embedded area in the first semiconductor layer to provide a frame area
Data Source
AI summary
An aspect of the present embodiment, there is provided a semiconductor device, including a first electrode, a first semiconductor layer having a first conductive type connected to the first electrode, a second semiconductor layer having a second conductive type contacted to the first semiconductor layer, a third semiconductor layer having the first conductive type, an impurity concentration of the third semiconductor layer being smaller than an impurity concentration of the second semiconductor layer, the third semiconductor layer contacting to the second semiconductor layer to be separated from the first semiconductor layer by the second semiconductor layer, a gate insulator provided on the second semiconductor layer, and the first semiconductor layer and the third semiconductor layer arranged at both sides of the second semiconductor layer, respectively, a gate electrode on the gate insulator; and a second electrode connected to the third semiconductor layer.