Multi-level Metal Gate Pad Overlap for Power MOSFET Active Area
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Solution Overview
Problem
The existing semiconductor device layouts face challenges in maximizing active area due to the large size of gate pads, which occupy a significant portion of the die and limit the active area, especially in small devices, where the inactive area under the gate pad restricts current conduction and heat transfer.
Innovation Solution
The solution involves overlapping metal layers to increase the active area without increasing the device size, using a second metal layer to extend the source bonding pad and improve heat transfer, and incorporating tie-down vias for better adhesion and reduced resistance, allowing for custom placement of external terminals and increased active area in power MOSFET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate pad is made large enough to accommodate bond wire or other attachment, then the bonding area is adequate, but the active area is limited because the gate pad takes up a large portion of the die
Solution Approach 1:
The patent applies multi-level metal layers to transition from a two-dimensional layout to a three-dimensional structure. The gate pad is formed in a second metal layer that overlaps with the source region in a first metal layer, allowing the bonding area to be increased vertically without consuming additional horizontal die area. This dimensional change enables both adequate bonding area and maximized active area to coexist.
Solution Approach 2:
The gate pad structure is nested within the overall device structure by placing it in an upper metal layer that overlaps the source region. The gate pad is coupled to the gate bus through vias that penetrate through intermediate dielectric layers, creating a nested configuration where the gate pad sits above the active source region without interfering with its function.
2Reliability
If the gate pad size is increased to provide adequate bonding area, then bonding is improved, but the inactive area under the gate pad increases which limits current conduction
Solution Approach 1:
By forming the gate pad in a second metal layer above the first metal layer containing the source region, the patent creates a vertical stacking configuration. This allows the gate pad to have adequate bonding area for reliable wire attachment while the source region beneath it remains fully active for current conduction, eliminating the trade-off between bonding reliability and current productivity.
3Area of stationary object
If the device size is kept small, then integration density is improved, but the active area is limited due to the relative size of the gate pad
Solution Approach 1:
The patent uses multi-level metal layers to stack the gate pad vertically above the source region, transforming the layout from two-dimensional to three-dimensional. This allows the device to maintain a compact footprint while maximizing the active area, as the gate pad no longer consumes horizontal space that could be used for active devices.
4Area of moving object
If metal layers are overlapped to increase active area, then active area is improved, but electrical isolation between the metal layers must be maintained
Solution Approach 1:
The patent introduces an inter-metal dielectric layer as an intermediary between the first metal layer (source region) and the second metal layer (gate pad). This dielectric layer provides the necessary electrical isolation to prevent short circuits while allowing the metal layers to overlap horizontally, thereby maximizing active area without compromising electrical integrity.
5Temperature
If the source bonding pad is extended to extremes of the device, then heat transfer and current capacity are improved, but the device complexity increases
Solution Approach 1:
The extended source bonding pad is formed in a first metal layer that can be arranged in complex two-dimensional patterns, while the gate pad in the second metal layer provides vertical overlap. This multi-level configuration allows the source bonding pad to extend to device extremes for improved heat dissipation and current capacity without adding significant structural complexity, as the extension is achieved through planar metal layer design rather than three-dimensional structures.
Data Source
AI summary
This document discusses, among other things, a semiconductor device including first and second conductive layers, the first conductive layer including a gate runner and a drain contact and the second conductive layer including a drain conductor, at least a portion of the drain conductor overlying at least a portion of the gate runner. A first surface of the semiconductor device can include a gate pad coupled to the gate runner and a drain pad coupled to the drain contact and the drain conductor.