Trench Power MOSFET Gate PIN Junction for Capacitance Reduction
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Solution Overview
Problem
High intrinsic gate-to-drain capacitance in trench power MOSFETs limits switching speed and makes them unfavorable for high-frequency circuits, as it increases switching loss and reduces packing density.
Innovation Solution
A manufacturing method for trench power MOSFETs that forms a PIN, P+/N−, or N+/P− junction in the gate, reducing effective capacitance by creating junction capacitance in series with parasitic capacitance through a specific doping structure and reverse bias, thereby minimizing gate-to-drain effective capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional trench gate structure is used, then packing density is improved, but intrinsic gate-to-drain capacitance increases which limits switching speed
Solution Approach 1:
The patent changes the electrical parameters of the gate structure by forming a PIN junction within the gate. This junction creates a depletion region that acts as an insulating barrier, effectively reducing the gate-to-drain capacitance while preserving the trench gate's high packing density advantage
Solution Approach 2:
The PIN junction serves as an intermediary element within the gate structure. The intrinsic layer and depletion region act as a mediator that blocks the capacitive coupling between gate and drain, reducing the effective capacitance without compromising the physical packing density
2Speed
If intrinsic gate-to-drain capacitance is reduced, then switching speed improves, but device complexity increases due to additional doping regions
Solution Approach 1:
The patent merges the capacitance reduction function with the existing gate structure by forming the PIN junction within the gate. This combines multiple functions (gate control and capacitance reduction) into a single integrated structure, avoiding the need for separate components and minimizing additional complexity
3Loss of energy
If switching loss is reduced through capacitance reduction, then energy efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary doping actions during the epitaxial growth process to form the PIN junction. By preparing the doping structure in advance during a well-controlled process, the manufacturing precision requirements are managed more effectively than if complex post-processing steps were required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces gate-to-drain effective capacitance, minimizing switching loss and enhancing switching speed, making trench power MOSFETs more suitable for high-frequency applications.
Implementation Method 1
Since a junction capacitance (Cj) of the PIN, P+/N− or N+/P− junction is generated under reverse bias, and the junction of capacitance is in series with the parasitic capacitance (Cp), the effective capacitance between the gate and the drain can be reduced
Data Source
AI summary
A manufacturing method of a trench power MOSFET is provided. In the manufacturing method, the trench gate structure of the trench power MOSFET is formed in the epitaxial layer and includes an upper doped region, a lower doped region and a middle region interposed therebetween. The upper doped region has a conductive type reverse to that of the lower doped region, and the middle region is an intrinsic or lightly-doped region to form a PIN, P+/N− or N+/P− junction. As such, when the trench power MOSFET is in operation, a junction capacitance formed at the PIN, P+/N− or N+/P− junction is in series with the parasitic capacitance. Accordingly, the gate-to-drain effective capacitance may be reduced.