III-V MOSFET Gate Dielectric Stability via Oxygen Plasma
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Solution Overview
Problem
III-V semiconductor compounds, such as GaAs, face challenges in forming reliable and stable insulated gate field effect transistors due to instabilities in semiconductor surfaces and dielectrics, leading to high sheet resistance and degradation over time, despite surface treatments which provide only temporary improvements.
Innovation Solution
A method involving the formation of a gallium oxide and gadolinium gallium oxide dielectric stack with a silicon nitride layer, treated with an oxygen plasma to reduce contamination and trap formation, resulting in a stable and low-sheet-resistance insulated gate field effect transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If surface treatments are applied to reduce sheet resistance, then initial device performance is improved, but the improvements are only temporary and devices revert to pre-treatment conditions
Solution Approach 1:
The patent applies preliminary action by performing plasma treatment on the gate dielectric surface before device operation to reduce surface states and trapped charge. This pre-treatment creates a stable, low-resistance state that persists through device operation, preventing the reversion to high sheet resistance conditions that plagues conventional approaches.
Solution Approach 2:
The patent changes the physical-chemical parameters of the gate dielectric surface through plasma exposure, modifying surface states, trapped charge distribution, and interface properties. These parameter changes create a stable surface condition that maintains low sheet resistance over time, addressing both the reliability and duration aspects of the contradiction.
2Reliability
If gallate dielectric layers are used for gate insulation, then insulated gate functionality is achieved, but bulk dielectric charge trapping increases series ON-resistance
Solution Approach 1:
The patent extracts or removes the harmful trapped charge from the gate dielectric through plasma treatment. By applying plasma to the gate dielectric surface, the treatment removes or neutralizes bulk dielectric charge trapping, thereby reducing the series ON-resistance while preserving the insulated gate functionality provided by the gallate dielectric layer.
Solution Approach 2:
The patent converts the harmful effect of charge trapping in the gallate dielectric into a beneficial outcome. Through plasma treatment, the previously harmful trapped charge is removed or neutralized, transforming the gate dielectric from a source of high series resistance into a stable, low-resistance insulated gate structure that maintains both functionality and performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach maintains low sheet resistance and enhances the longevity of device performance by reducing surface states and trapped charge, as demonstrated by X-ray Photoelectron Spectroscopy data, achieving high III-V MOSFET performance.
Implementation Method 1
treated with an oxygen plasma to reduce contamination and trap formation
Data Source
AI summary
An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.