Selective MOSFET Gate Recessing for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In modern CMOS technology, parasitic transistor gate electrode capacitance poses a significant limit to device performance, especially with device scaling and the introduction of high-k gate dielectrics, and there is a need to reduce parasitic capacitance and tune gate electrode properties effectively.
Innovation Solution
The solution involves selectively recessing transistor gate electrodes to different z-heights, allowing for modulation of parasitic capacitive area and other structural attributes, enabling differentiation of gate electrode properties based on circuit demands, such as conductivity type or function within a circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device scaling continues to reduce feature pitch, then transistor density increases, but parasitic gate electrode capacitance increases and limits device performance
Solution Approach 1:
The patent applies local quality by differentiating gate electrode z-heights based on circuit function. Logic transistors have recessed gates to minimize parasitic capacitance for high-speed switching, while analog transistors have non-recessed gates to maximize capacitance for stability. This localized structural differentiation resolves the contradiction by optimizing each region's gate structure for its specific functional requirements rather than using a uniform approach across the entire device.
2Reliability
If high-k gate dielectrics are introduced to improve transistor performance, then device performance improves, but parasitic capacitances increase due to high-k films in regions other than the channel-gate interface
Solution Approach 1:
The patent applies the extraction principle by selectively removing high-k gate dielectric material from specific regions where it would create unwanted parasitic capacitance. The high-k dielectric is retained only at the channel-gate interface where it provides beneficial performance enhancement, while being eliminated from overlap regions and other areas where it would contribute to parasitic effects. This selective extraction resolves the contradiction by preserving the useful function while eliminating the harmful side effect.
3Ease of manufacture
If all gate electrodes are at the same z-height, then manufacturing is simplified, but selective tuning of gate electrode properties for different circuit functions is not possible
Solution Approach 1:
The patent applies segmentation by dividing the gate electrode structure into function-specific segments with different z-heights. Rather than treating all gate electrodes as a single uniform structure, the invention segments them into logic transistor gates (recessed) and analog transistor gates (non-recessed), each optimized for its specific function. This segmentation enables selective property tuning while maintaining manufacturing feasibility through a systematic, multi-step fabrication process.
4Object-generated harmful factors
If gate electrode z-height is varied to reduce parasitic capacitance, then parasitic capacitance decreases, but device complexity increases
Solution Approach 1:
The patent applies the dimensionality change principle by utilizing the z-height dimension to control parasitic capacitance. Instead of trying to reduce parasitic effects through planar geometry modifications alone, the invention introduces vertical dimension variation through selective gate recessing. This adds a new degree of freedom for parasitic control that, while increasing structural complexity, does so in a controlled and systematic manner that enables significant parasitic reduction without proportionally increasing overall device complexity.
Data Source
AI summary
Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.