MOSFET Gate Resistor Layout for Lower Chip Temperature Rise

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Solution Overview

Problem

In power modules with transistor chips, embedding a gate resistor to suppress resonance and ensure uniform current flow leads to increased module size and reduced flexibility in chip arrangement, and the resistor's heat generation causes temperature fluctuations and potential destruction of the transistor.

Innovation Solution

A semiconductor device with a MOSFET structure that includes a polycrystalline silicon layer acting as the gate resistor, where the first opening area for connecting the gate electrode pad is larger than the second opening area for connecting the gate wiring layer, facilitating better heat dissipation and reducing temperature rise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a gate resistance component is connected outside the transistor chip, then resonance suppression and uniform current flow are achieved, but the power module size increases and arrangement flexibility is reduced

Engineering Contradiction:
Improveresonance suppressionVSAvoidpower module size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The gate resistance component is merged with the transistor chip structure by embedding it in the insulating layer on the chip surface. This integration allows the resistance component to be formed using the same semiconductor manufacturing processes as the transistor itself, eliminating the need for separate external components and reducing overall module size while maintaining resonance suppression functionality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The gate resistance component is nested within the insulating layer of the transistor chip structure. The resistance layer is positioned between the gate electrode pad and the gate wiring layer, effectively hiding the resistance component within the existing chip architecture rather than adding external components.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If a gate resistance component is connected outside the transistor chip, then resonance suppression and uniform current flow are achieved, but the degree of freedom in arrangement of transistor chips is reduced

Engineering Contradiction:
Improveuniform current flowVSAvoidarrangement flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

By integrating the gate resistance component directly into the transistor chip structure, the design eliminates external connection requirements, thereby restoring full arrangement flexibility for transistor chips in the power module while maintaining uniform current flow characteristics.

Inventive Principle:
Principle #5Merging (Combining)

3Area of stationary object

If a gate resistor is embedded in the transistor chip, then module size is reduced and arrangement flexibility is improved, but heat generation causes temperature fluctuations and potential transistor destruction

Engineering Contradiction:
Improvepower module sizeVSAvoidtemperature rise
Core Design Contradiction:
Area of stationary objectVSTemperature

Solution Approach 1:

The insulating layer is designed with different local properties: regions with larger opening areas beneath the gate electrode pad to enhance heat dissipation, and regions with smaller opening areas in other positions to maintain electrical insulation and resistance functionality. This local differentiation allows heat management without compromising the embedded resistance structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The insulating layer acts as an intermediary structure that serves multiple functions: providing electrical insulation between conductive layers, embedding the gate resistance component, and managing heat dissipation through controlled opening areas that allow thermal pathways while maintaining electrical isolation.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Area of stationary object

If a gate resistor is embedded in the transistor chip, then module size is reduced and arrangement flexibility is improved, but temperature fluctuations may cause transistor destruction

Engineering Contradiction:
Improvepower module sizeVSAvoidtransistor stability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The insulating layer is designed with different local properties: regions with larger opening areas beneath the gate electrode pad to enhance heat dissipation, and regions with smaller opening areas in other positions to maintain electrical insulation and resistance functionality. This local differentiation allows heat management without compromising the embedded resistance structure.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively suppresses temperature rise and maintains transistor characteristics by enhancing heat dissipation through the gate electrode pad, preventing fluctuations and destruction.

Implementation Method 1

the first opening area of the at least one first opening is larger than a second opening area of the at least one second opening, wherein the electrode pad and the first polycrystalline silicon layer are electrically connected via an inside of the at least one first opening, the wiring layer and the first polycrystalline silicon layer are electrically connected via an inside of the at least one second opening

Methodology Applied
Scientific EffectHeat dissipation: Convection

Data Source

PatentUS11756863B2Semiconductor device
Publication Date: 2023.09.12 KK TOSHIBA
  • US11756863B2 patent drawing
  • US11756863B2 patent drawing
  • US11756863B2 patent drawing

AI summary

According to an embodiment, provided is a semiconductor device includes a semiconductor layer; a first electrode; a second electrode; an electrode pad; a wiring layer electrically connected to the gate electrode; a first polycrystalline silicon layer electrically connected to the electrode pad and the wiring layer; and an insulating layer provided between the first polycrystalline silicon layer and the electrode pad and between the first polycrystalline silicon layer and the wiring layer and having a first opening and a second opening. The electrode pad and the first polycrystalline silicon layer are electrically connected via an inside of the first opening. The wiring layer and the first polycrystalline silicon layer are electrically connected via an inside of the second opening, A first opening area of the first opening is larger than a second opening area of the second opening.