Segmented MOSFET Gate Structure for RF Switch Coff*Ron Trade-Off
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Solution Overview
Problem
MOSFET transistors used in RF signal switching applications face challenges in optimizing the trade-off between parasitic capacitance and on-state resistance, which affects their performance and efficiency, particularly in maintaining high voltage handling capabilities without increasing the complexity and cost of manufacturing processes.
Innovation Solution
The design incorporates a gate region with a unique structure, featuring a first portion and a second portion with varying lengths and thicknesses of the gate insulator, along with a lightly-doped drain region and an oxide layer, to minimize overlap capacitance and on-state resistance, achieved through specific etching steps and material deposition techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate region is made longer to reduce on-state resistance, then the on-state resistance decreases, but the parasitic capacitance increases
Solution Approach 1:
The gate region is divided into two distinct portions: a first portion extending over the channel region and a second portion positioned adjacent to the first portion but not overlapping the channel. This segmentation allows each portion to serve different functions - the first portion controls the channel while the second portion provides capacitance reduction, thereby resolving the contradiction between maintaining low on-state resistance and minimizing parasitic capacitance.
Solution Approach 2:
Different regions of the gate structure are given different properties - the first portion of the gate region is positioned to provide effective channel control for low on-state resistance, while the second portion is strategically positioned to minimize overlap with the channel region, thereby reducing parasitic capacitance. This local differentiation allows simultaneous optimization of both parameters.
2Object-generated harmful factors
If the gate insulator thickness is increased to reduce parasitic capacitance, then the parasitic capacitance decreases, but the voltage handling capability is reduced
Solution Approach 1:
The gate insulator structure is made non-uniform with different thicknesses in different regions. The first region has a first thickness optimized for voltage handling, while the second region has a second thickness optimized for capacitance reduction. This local differentiation allows the structure to simultaneously achieve both low parasitic capacitance and high voltage handling capability without compromise.
Solution Approach 2:
Instead of uniformly increasing gate insulator thickness throughout, the invention varies the thickness in the lateral dimension across different regions. This dimensional approach allows optimization of electrical properties in different spatial locations, achieving both low capacitance and high voltage tolerance by positioning thinner and thicker regions appropriately.
3Object-generated harmful factors
If the gate region is made shorter to reduce parasitic capacitance, then the parasitic capacitance decreases, but the on-state resistance increases
Solution Approach 1:
By segmenting the gate region into two portions with different functions, the invention overcomes the limitation of a single uniform gate length. The first portion maintains adequate overlap with the channel for low on-state resistance, while the second portion extends adjacent to the first portion to provide additional capacitance reduction without proportionally increasing resistance, thus resolving the contradiction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and on-state resistance, enhancing the performance of MOSFET transistors for RF signal switching while maintaining high voltage handling capabilities without adding complex manufacturing steps, thus improving the trade-off between Coff*Ron and voltage RF Vmax.
Implementation Method 1
comprises, for example, consists of, a layer of reoxidation of the gate region, for example of thermal reoxidation
Data Source
AI summary
A MOSFET transistor includes, on a semiconductor layer, a stack of a gate insulator and of a gate region on the gate insulator. The gate region has a first gate portion and a second gate portion between the first gate portion and the gate insulator. The first gate portion has a first length in a first lateral direction of the transistor. The second gate portion has a second length in the first lateral direction that is shorter than the first length.