MOSFET Gate Polysilicon Segmentation for Leakage Reduction
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Solution Overview
Problem
Conventional ESD protection circuits in integrated circuits suffer from significant leakage current due to parasitic bipolar transistors, which contributes to power dissipation and needs to be reduced.
Innovation Solution
A MOSFET structure with a gate polysilicon region configured as a N+/P+/N+ structure, where the P+ sub-region determines the threshold voltage, reducing leakage current by increasing the threshold voltage and using a silicide block to manage doping and reduce current crowding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional NMOS structure with parasitic bipolar transistor is used for ESD protection, then ESD discharge capability is achieved, but leakage current increases significantly
Solution Approach 1:
The gate polysilicon region is segmented into three doped sub-regions (first, second, and third sub-regions with different doping types and concentrations), allowing independent control of threshold voltage and leakage current characteristics while maintaining ESD protection functionality
Solution Approach 2:
Different sub-regions of the gate polysilicon are doped with different doping types and concentrations to create localized properties: the first and second sub-regions adjacent to source/drain provide one set of electrical characteristics, while the third sub-region between them provides different characteristics, enabling optimized threshold voltage and reduced leakage current in specific areas
2Loss of energy
If the threshold voltage is increased to reduce leakage current, then power dissipation decreases, but ESD discharge capability may be affected
Solution Approach 1:
The threshold voltage is increased by changing the doping parameters of the gate polysilicon region, specifically by introducing the three-sub-region structure with different doping types and concentrations, which modifies the electrical characteristics to reduce leakage current while preserving ESD functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MOSFET structure effectively lowers leakage current by increasing the threshold voltage, reducing power dissipation and enhancing ESD robustness, while maintaining minimal processing time and cost.
Implementation Method 1
The gate polysilicon region includes a first sub-region of the first doping type, a second sub-region of the first doping type, and a third sub-region of a second doping type
Implementation Method 2
implanting ions of a first doping type through the first and second openings, to form a source region in the semiconductor substrate, a drain region in the semiconductor substrate, a first sub-region of the gate polysilicon region laterally adjacent to the source region, and a second sub-region of the gate polysilicon region laterally adjacent to the drain region
Data Source
AI summary
A MOSFET fabricated in a semiconductor substrate, includes: a gate oxide region formed atop the semiconductor substrate; a gate polysilicon region formed on the gate oxide region; a source region of a first doping type formed in the semiconductor substrate and located at a first side of the gate polysilicon region; and a drain region of the first doping type formed in the semiconductor substrate and located at a second side of the gate polysilicon region. The gate polysilicon region has a first sub-region of the first doping type, a second sub-region of the first doping type, and a third sub-region of a second doping type, wherein the first sub-region is laterally adjacent to the source region, the second sub-region is laterally adjacent to the drain region, and the third sub-region is formed laterally between the first and second sub-regions.