MOSFET Source Contact and Gate Shield Layout for Pitch Reduction
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Solution Overview
Problem
The challenge in designing semiconductor power devices is to achieve high breakdown voltage while maintaining low on-state resistance, as increasing breakdown voltage typically increases on-state resistance due to the lightly doped drain (LDD) region's design limitations.
Innovation Solution
The semiconductor structure incorporates a lateral diffusion field effect transistor (LDFET) with a gate shield structure that allows for a narrower cell pitch by defining a bottom recess and a flared section in the gate shield, enabling the formation of a source contact with a narrower bottom portion than the minimum contact feature size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the lightly doped drain (LDD) region is designed to increase breakdown voltage, then the breakdown voltage is improved, but the on-state resistance increases
Solution Approach 1:
The source contact is divided into two distinct portions: a first portion with a first width and a second portion with a second width narrower than the first width. This segmentation allows different regions of the contact to serve different functions - the wider first portion provides adequate current carrying capacity while the narrower second portion enables closer spacing to adjacent structures, effectively resolving the contradiction between maintaining low on-state resistance and achieving high breakdown voltage through pitch reduction
Solution Approach 2:
The gate shield structure incorporates a bottom recess portion with specific dimensional characteristics (width and depth) that create localized electric field modulation. This local structural modification allows the shield to effectively manage electric field distribution in the LDD region, maintaining high breakdown voltage while enabling the source contact to achieve narrower spacing for reduced on-state resistance
2Reliability
If the source contact width is reduced to decrease on-state resistance, then the on-state resistance is improved, but the manufacturing precision requirements increase due to minimum contact feature size constraints
Solution Approach 1:
The gate shield structure is extended into the vertical dimension by incorporating a bottom recess portion with a specific depth. This dimensional extension allows the source contact to achieve an effective narrower width at the critical interface region without violating minimum contact feature size constraints in the planar dimension, thereby reducing on-state resistance while maintaining manufacturability
Solution Approach 2:
The narrower second portion of the source contact is positioned within the structural envelope defined by the gate shield's bottom recess. This nested configuration allows the contact to achieve its narrowed dimension in a protected and defined space, ensuring manufacturing precision is maintained while achieving the desired electrical performance
Data Source
AI summary
A semiconductor structure that includes at least one lateral diffusion field effect transistor is described. The structure includes a source contact and a gate shield that enables the line width of an ohmic region that electrically connects the source/body region to the gate shield to be smaller than the minimum contact feature size. The gate shield defines a bottom recess for forming a narrower bottom portion of the source contact, and a section that flares outward with distance from the ohmic region to extend above and laterally beyond the ohmic region. By providing a wider area for the source contact, the flared portion of the gate shield allows the portion of the gate shield that contacts the ohmic region to be narrower than the minimum contact feature size. As a result, the cell pitch of the lateral diffusion field effect transistor can be reduced.