MOSFET Gate Spacer Profile for Scaled Device Reliability
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in electric and reliability characteristics.
Innovation Solution
A semiconductor device is designed with a gate spacer that includes an upper portion with a first thickness and a lower portion with a second thickness, where the second thickness is larger than the first thickness, and the lower portion is located at a level lower than the uppermost semiconductor pattern. This configuration is applied in both PMOSFET and NMOSFET regions, with varying thicknesses of the gate spacers to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to reduce pattern size and design rule, then device integration density is improved, but operational properties deteriorate
Solution Approach 1:
The gate spacer is designed with non-uniform thickness, having a first thickness at the upper portion and a second thickness at the lower portion that is greater than the first thickness. This local variation in thickness provides enhanced protection at the lower portion where unetch defects and pitting failures are more likely to occur, while maintaining appropriate dimensions at the upper portion.
Solution Approach 2:
The thicker lower portion of the gate spacer serves as a preventive measure against unetch defects and pitting failures that may occur during subsequent processing steps. By providing extra thickness at the vulnerable lower portion beforehand, the structure is cushioned against potential defects before they can compromise device operation.
2Reliability
If gate spacer thickness is increased to prevent unetch defects and pitting failures, then reliability is improved, but device complexity increases
Solution Approach 1:
Rather than uniformly increasing the gate spacer thickness throughout, the invention applies increased thickness only at the lower portion where it is most needed for preventing unetch defects and pitting failures. This localized approach improves reliability while minimizing the increase in overall device complexity.
Data Source
AI summary
Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an active pattern on a substrate, a device isolation layer provided on the substrate to define the active pattern, a pair of source/drain patterns on the active pattern and a channel pattern therebetween, the channel pattern including semiconductor patterns which are stacked and are spaced apart from each other, a gate electrode crossing the channel pattern, and a gate spacer on a side surface of the gate electrode. The gate spacer located on the device isolation layer includes an upper portion with a first thickness and a lower portion with a second thickness. The second thickness is larger than the first thickness, and the lower portion of the gate spacer is located at a level lower than the uppermost one of the semiconductor patterns.