MOSFET Gate Structure for Threshold Voltage Control
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Solution Overview
Problem
Existing MOSFET fabrication methods face challenges in increasing threshold voltage at active corners, leading to current leakage and reduced reliability due to increased process complexity and misalignment issues in counterdoping processes.
Innovation Solution
A MOSFET design featuring a gate structure with a combination of undoped or lightly-doped polysilicon and doped polysilicon layers, where the undoped polysilicon layer covers the channel edge and the doped polysilicon layer covers the rest of the channel region, allowing for increased threshold voltage without additional masking steps and accommodating misalignment, thereby simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If counterdoping is performed to increase threshold voltage at active corners, then device reliability improves, but process complexity increases due to additional masking steps
Solution Approach 1:
The gate polysilicon layer is segmented into two distinct regions: a first region that is counterdoped to increase threshold voltage at active corners, and a second region that remains undoped or lightly-doped to maintain low threshold voltage in the channel region. This segmentation allows selective application of counterdoping only where needed, avoiding the complexity of masking the entire gate structure while still achieving improved device reliability.
2Manufacturing precision
If counterdoping depth is increased to form depleted regions near the gate interface, then threshold voltage increases, but misalignment causes oppositely-doped regions that lead to short circuits
Solution Approach 1:
The gate polysilicon layer is given non-uniform doping characteristics: the first region (at active corners) is counterdoped with high doping concentration to increase threshold voltage, while the second region (over the channel) is undoped or lightly-doped to maintain proper threshold voltage. This local quality differentiation ensures that counterdoping effects are confined to specific locations, preventing misalignment-induced short circuits while achieving the desired threshold voltage increase at active corners.
3Manufacturing precision
If additional masking steps are added to protect polysilicon gate regions, then doping precision improves, but fabrication time and cost increase
Solution Approach 1:
The gate polysilicon layer is formed with predetermined non-uniform doping characteristics through selective counterdoping of the first region before final gate fabrication steps. By establishing the doping profile in advance during the polysilicon formation process, the need for additional masking steps to protect specific gate regions is eliminated, thereby maintaining doping precision while improving fabrication efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability of MOSFETs by increasing the threshold voltage at active corners, reducing process complexity, and allowing for practical fabrication with improved alignment tolerances, thus preventing current leakage and short circuits.
Implementation Method 1
the first polysilicon layer being a layer of undoped polysilicon, lightly-doped polysilicon or a combination thereof... the lightly-doped polysilicon being implanted with ions of a same conductivity type as ions implanted in the second polysilicon layer
Implementation Method 2
the lightly-doped polysilicon being implanted with ions of a same conductivity type as ions implanted in the second polysilicon layer as well as in the source and drain regions
Data Source
AI summary
A metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for fabricating the MOSFET are disclosed. In the method, after a gate is formed by etching a deposited undoped or lightly-doped polysilicon layer, with the portions of the gate above channel edge between a channel region and STI region being protected, ions are doped into the remaining gate portion during source/drain implantation. As a result, each of the gate portions above channel edge is constructed of a doped second polysilicon layer stacked with undoped (or lightly-doped) first polysilicon layers, while the remaining gate portion is simply constituted by the doped second polysilicon layer. This can increase a threshold voltage of the MOSFET at channel edge. Optionally, before the gate is formed by etching the polysilicon, the portions of the polysilicon above the channel edge may be protected, followed by doping ions into the remaining portions of the polysilicon.