MOSFET Gate Voltage Limiter for ESD Protection
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Solution Overview
Problem
Conventional integrated circuits face challenges in efficiently protecting against electrostatic discharge (ESD) due to the limitations of large MOSFET transistors required for effective ESD current dissipation, which occupy significant chip space and have low current efficiency, making them difficult to position and fabricate effectively.
Innovation Solution
An ESD protection circuit incorporating a MOSFET with a voltage limiter that limits the gate voltage during an ESD event, leveraging parasitic current to enhance current conduction by inducing a base current within the transistor, thereby improving ESD current shunting efficiency without requiring fabrication process changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large MOSFET transistors are used for ESD current dissipation, then ESD protection capability is improved, but chip space occupied increases and current efficiency decreases
Solution Approach 1:
The patent changes the operating parameters of the MOSFET by introducing a voltage limiter that constrains the gate voltage to a specific range (between ground and Vdd). This parameter change enables the MOSFET to operate in a more efficient regime, inducing parasitic current flow that enhances ESD protection capability while reducing the required transistor size and chip space occupation.
2Reliability
If large MOSFET transistors are used for ESD current dissipation, then ESD protection capability is improved, but device complexity and positioning difficulty increase
Solution Approach 1:
By changing the gate voltage parameter through the voltage limiter mechanism, the patent simplifies the MOSFET design requirements. The voltage limiter ensures the gate voltage remains within acceptable bounds, which simplifies fabrication and positioning constraints while maintaining robust ESD protection capability.
Solution Approach 2:
The voltage limiter acts as an intermediary component that mediates between the ESD event and the MOSFET gate. It controls the gate voltage to induce parasitic current while preventing excessive voltage that would complicate the MOSFET design, thereby reducing overall device complexity and fabrication difficulty.
3Reliability
If MOSFET operates in surface mode with full Vdd gate voltage, then ESD current shunting is achieved, but current efficiency is limited by drain saturation current
Solution Approach 1:
The patent changes the gate voltage parameter from full Vdd to a limited range (between ground and Vdd) using a voltage limiter. This parameter change induces parasitic current flow in the MOSFET, which significantly improves current efficiency by enabling the device to shunt ESD current more effectively without being limited by drain saturation current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution achieves up to 50% better ESD current conduction performance compared to traditional designs, effectively protecting integrated circuits from ESD events while reducing the size and complexity of MOSFETs needed, thus enhancing current efficiency and reducing chip space requirements.
Implementation Method 1
limiting a gate turn on voltage of a clamp transistor of an ESD protection circuit during the ESD event... inducing a base current within the transistor to effectively shunt a current arising from the ESD event
Data Source
AI summary
Integrated circuits with electrostatic discharge (ESD) protection and methods of providing ESD protection in an integrated circuit are provided. An ESD protection circuit the ESD protection circuit may incorporate a transistor, such as a MOSFET, and a voltage limiter coupled to a gate of the transistor. The voltage limiter may be configured such that with an ESD disturbance on the voltage supply rail, Vdd, a gate voltage of the transistor of the ESD protection circuit is held below the supply voltage (Vdd) inducing base current, Isub, within the transistor to effectively shunt a current arising from the ESD event from the voltage supply rail Vdd to the voltage supply rail Vss.