MOSFET Gate Work Function Engineering via Segmented Metal Features

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Solution Overview

Problem

Current semiconductor devices, such as MOSFETs, face challenges in independently tuning short channel effects and threshold voltage due to the need to control the work function of the entire gate region, which limits the freedom of tuning both parameters simultaneously.

Innovation Solution

A semiconductor device with a gate stack comprising a high k dielectric layer and two metal features with different work functions, where the first metal feature is formed using a gate-first method and the second metal feature is formed using a gate-last method, allowing for independent control of short channel effects and threshold voltage by embedding the second metal feature within the first metal feature.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the work function of the entire gate region is tuned to control threshold voltage, then the threshold voltage is controlled, but the short channel control and Vt target cannot be tuned independently

Engineering Contradiction:
Improvethreshold voltage controlVSAvoidindependent tuning freedom
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The gate electrode is divided into multiple segments with different work functions. The gate stack includes a first metal gate electrode with a first work function and a second metal gate electrode with a second work function different from the first. This segmentation allows independent control of threshold voltage and short channel effects by adjusting the work function of each segment separately, resolving the contradiction between precise threshold voltage control and independent tuning freedom.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the gate electrode are assigned different work function characteristics. The first metal gate electrode region provides one work function value while the second metal gate electrode region provides a different work function value. This local quality differentiation enables independent optimization of threshold voltage (controlled by one region) and short channel effects (controlled by another region), achieving both tuning goals simultaneously.

Inventive Principle:
Principle #3Local quality

2Device complexity

If a single metal gate is used, then the device structure is simple, but both short channel control and threshold voltage cannot be tuned independently

Engineering Contradiction:
Improvegate structureVSAvoidparameter tuning precision
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The gate electrode is segmented into multiple metal gate electrodes with different work functions. This segmentation increases device complexity but enables precise independent control of threshold voltage and short channel effects, resolving the contradiction between structural simplicity and parameter tuning precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate electrode uses composite metal structures with different work function materials. This composite approach maintains reasonable structural complexity while achieving the precision needed for independent tuning of multiple device parameters, balancing device complexity and manufacturing precision.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS8679926B2Local charge and work function engineering on MOSFET
Publication Date: 2014.03.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8679926B2 patent drawing
  • US8679926B2 patent drawing
  • US8679926B2 patent drawing

AI summary

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.