Semiconductor Impurity Layout for Stable MOSFET Isolation Breakdown
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Solution Overview
Problem
The existing structure of semiconductor devices with impurity regions struggles to maintain reliability when the cell region's structure is changed, leading to potential breakdown voltage issues and electrical isolation challenges.
Innovation Solution
A semiconductor device design featuring a specific configuration of impurity regions and an element isolation portion with a trench and dielectric film, where the element isolation portion is located in the second impurity region and spaced apart from the junction interface, and a recombination promoting layer is formed to enhance recombination and reduce parasitic breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the structure of the cell region is changed, then new device configurations can be achieved, but the existing peripheral region structure may not fit, leading to reduced breakdown voltage and reliability
Solution Approach 1:
The patent applies local quality by differentiating the impurity regions into specific types (first, second, third, fourth, and fifth impurity regions) with different conductivity types and depths. The second impurity region extends deeper than the element isolation portion to specifically address the junction interface area, while the fifth impurity region is positioned to contact the second impurity region. This localized differentiation ensures that each region performs its specific function to maintain breakdown voltage regardless of cell region structure changes.
Solution Approach 2:
The patent segments the impurity regions into multiple distinct zones with different properties. The first impurity region is formed from the upper surface to a first depth, the second impurity region extends deeper to surround the cell region, the third impurity region surrounds the second impurity region, and the fourth and fifth impurity regions are positioned to contact specific interfaces. This segmentation allows each region to independently maintain electrical connectivity and breakdown voltage characteristics.
2Manufacturing precision
If the element isolation portion is positioned closer to the junction interface, then manufacturing precision can be improved, but electrical connectivity and breakdown voltage stability deteriorate
Solution Approach 1:
The patent introduces the fifth impurity region as an intermediary between the element isolation portion and the fourth impurity region. The fifth impurity region is positioned to contact the second impurity region and is located on the fourth impurity region, creating a buffer zone that ensures electrical connectivity even when the element isolation portion is positioned at different depths. This intermediary region maintains the electrical path and breakdown voltage characteristics independent of the exact element isolation portion positioning.
3Object-affected harmful factors
If impurity regions are formed to ensure electrical isolation, then noise resistance is improved, but parasitic breakdown voltage may occur at junction interfaces
Solution Approach 1:
The patent changes the parameters of the impurity regions by forming the second impurity region to extend deeper than the element isolation portion, and positioning the fifth impurity region to contact the second impurity region. This parameter change in the depth and positioning of impurity regions modifies the electrical characteristics at the junction interface, suppressing parasitic breakdown voltage while maintaining the electrical isolation and noise resistance provided by the impurity regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the reliability of the semiconductor device by ensuring reliable electrical isolation and maintaining high breakdown voltage, even when the cell region's structure is altered, by promoting recombination across the junction interface.
Implementation Method 1
a recombination promoting layer is formed to enhance recombination and reduce parasitic breakdown voltage
Data Source
AI summary
A semiconductor device includes a cell region in which MISFETs are formed, and a peripheral region surrounding the cell region in plan view. In the cell region and the peripheral region, an n-type impurity region is formed in a semiconductor substrate. In the semiconductor substrate, an element isolation portion, a p-type impurity region, and an n-type impurity region are formed in the peripheral region so as to surround the cell region in plan view. A p-type impurity region and an n-type impurity region are formed in the semiconductor substrate in the cell region so as to contact the impurity region. The element isolation portion is located in the impurity region and is spaced apart from a junction interface between the impurity region and the impurity region.