MOSFET Inner Gate Spacer Layout for Scaled Device Reliability
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Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of metal oxide semiconductor field effect transistors (MOSFETs) deteriorate, necessitating improved methods to enhance electrical performance and reliability.
Innovation Solution
A semiconductor device design featuring distinct inner gate spacers with varying thicknesses between source/drain patterns and gate electrodes, including a first inner gate spacer with a thickness ranging from 2.5 to 3 nm and a second inner gate spacer with a thickness ranging from 1.5 to 2 nm, to maintain optimal spacing and reduce electrical interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to increase integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The gate electrode is divided into multiple segments (first gate electrode and second gate electrode) positioned at different heights, allowing independent optimization of control for different channel regions. This segmentation enables improved electrical characteristics while maintaining high integration density.
Solution Approach 2:
The patent introduces a vertical dimension to the gate structure by positioning gate electrodes at different heights above the channel. This three-dimensional gate configuration allows better electrical control of the channel without increasing planar footprint, thus maintaining high integration while improving operating characteristics.
2Area of stationary object
If spacing between source/drain patterns and gate electrodes is reduced to minimize device area, then integration density increases, but electrical interference increases
Solution Approach 1:
By positioning gate electrodes at different vertical heights, the patent creates spatial separation in the vertical dimension while maintaining close horizontal spacing. This dimensional separation reduces electrical interference between the gate and source/drain patterns without increasing the overall device footprint.
Solution Approach 2:
The patent applies different gate electrode configurations to different regions of the device. The first gate electrode is positioned closer to the first source/drain pattern while the second gate electrode is positioned closer to the second source/drain pattern, optimizing local electrical characteristics and minimizing interference in each region.
Data Source
AI summary
Disclosed is a semiconductor device comprising a substrate including first and second active patterns, first and second channel patterns on the first and second active patterns and each including first and second semiconductor patterns, first source/drain patterns connected to the first channel pattern, second source/drain patterns connected to the second channel pattern, a first inner gate electrode between neighboring first semiconductor patterns, a second inner gate electrode between neighboring second semiconductor patterns, a first inner gate spacer between the first inner gate electrode and the first source/drain pattern, and a second inner gate spacer between the second inner gate electrode and the second source/drain pattern. The first inner gate spacer has a first thickness. The second inner gate spacer has a second thickness. The first thickness is greater than the second thickness.