MOSFET Insulator Segmentation for Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
MOSFET devices experience increased leakage current and reduced control over the channel due to short channel effects, particularly Drain Induction Barrier Lower (DIBL) effects, which hinder device performance and integration in Very Large Scale Integrated Circuits (VLSIC).
Innovation Solution
Forming insulators on both sides of the gate in the semiconductor substrate, located under the gate by 60-70 nm with a width of 15-25 nm, which increases the dielectric constant between source and drain regions, reducing capacitance coupling and effectively controlling leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel length is decreased to enhance gate control, then the gate control ability is improved, but the leakage current increases due to DIBL effects
Solution Approach 1:
The patent segments the channel region by introducing insulator structures (such as silicon oxide or silicon nitride) at specific locations beneath the gate, dividing the continuous channel into separated regions. This segmentation prevents direct carrier flow between source and drain, reducing leakage current while maintaining gate control over the active channel portions.
Solution Approach 2:
The patent introduces insulator structures as intermediary elements between the source and drain regions. These insulators act as mediators that block the harmful DIBL effect and prevent punch-through leakage, while allowing the gate to maintain control over the channel through the insulator layer.
2Productivity
If the channel length is decreased to improve device integration, then the integration level is enhanced, but the threshold voltage decreases due to severe DIBL effects
Solution Approach 1:
By segmenting the channel with insulator structures, the patent maintains a physically short channel for high integration density while creating electrically separated regions that prevent the cumulative DIBL effect from reducing threshold voltage. Each segment can be independently controlled by the gate.
Solution Approach 2:
The patent changes the dielectric parameters by introducing high-k insulator materials in specific regions beneath the gate. This modifies the electric field distribution and potential profile, maintaining threshold voltage despite reduced channel length by altering the local electrical parameters rather than the geometric dimensions.
3Object-generated harmful factors
If insulators are formed between source and drain regions to reduce leakage current, then leakage current is suppressed, but device complexity increases
Solution Approach 1:
The patent merges the insulator formation process with existing fabrication steps such as spacer formation or gate dielectric deposition. By combining multiple functions into single process steps, the structural complexity is reduced while still achieving leakage current suppression through the insulator structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses leakage current and enhances device performance by reducing the negative effects of DIBL, allowing for better control over the channel and improved integration in VLSIC.
Implementation Method 1
By formation of insulators between the source and drain regions, the dielectric constant between the source and drain regions can be effectively increased and the capacitance coupling can be decreased
Implementation Method 2
epitaxially growing a silicon layer to fill into the second vacancy with the silicon on both sides of the second vacancy as a seed layer
Data Source
AI summary
Provided is a MOSFET, comprising: a substrate (100); a gate stack (500) on the substrate (100); source/drain regions (305) in the substrate on both sides of the gate stack (500); an interlayer dielectric layer (400) covering the source/drain regions; and source/drain extension regions (205) under edges on both sides of the gate stack (500); wherein insulators, which are not connected each other, are formed beneath the source/drain extension regions (205) under edges on both sides of the gate stack (500). By means of the MOSFET in the present disclosure, negative effects induced by DIBL on device performance can be effectively reduced.