Power MOSFET Interconnect Structure for Low RDSON

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Solution Overview

Problem

Power MOSFETs face a challenge in achieving low RDSON (resistance between the drain and source terminals) due to the concentration of drain and source current conduction paths being compromised by the space required for gate terminals in semiconductor packages.

Innovation Solution

The development of a semiconductor device with an interconnect structure that includes stacked intermediate conductive layers and source planes, along with drain islands, to reduce resistance by distributing current density effectively across the source and drain planes, thereby minimizing the impact of gate terminal placement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If gate terminals are placed in semiconductor packages, then the power MOSFET can be controlled, but the drain and source current conduction paths become concentrated and RDSON increases

Engineering Contradiction:

Improvepower MOSFET controllabilityVSAvoidRDSON

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces intermediate conductive layers stacked in the vertical dimension between the drain and source planes. This multi-layer conductive structure distributes current conduction paths through multiple horizontal planes, effectively transforming a two-dimensional current path into a three-dimensional conduction network, thereby reducing current density concentration and RDSON while accommodating gate terminal requirements

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If current conduction paths are concentrated to reduce package size, then package footprint is reduced, but RDSON increases due to higher current density

Engineering Contradiction:

Improvepackage footprintVSAvoidRDSON

Core Design Contradiction:

Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent embeds multiple intermediate conductive layers within the vertical structure of the power MOSFET, nesting these conductive planes between the drain and source regions. This nested multi-layer configuration allows current to flow through multiple horizontal conductive planes stacked vertically, effectively increasing the total conduction area without expanding the package footprint, thus reducing RDSON while maintaining compact dimensions

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS9640638B2Semiconductor device and method of forming a power MOSFET with interconnect structure to achieve lower RDSON

Publication Date: 2017.05.02 GREAT WALL SEMICONDUCTOR CORP

AI summary

A semiconductor device has a substrate and gate structure over the substrate. A source region is formed in the substrate adjacent to the gate structure. A drain region in the substrate adjacent to the gate structure opposite the source region. An interconnect structure is formed over the substrate by forming a conductive plane electrically connected to the source region, and forming a conductive layer within openings of the conductive plane and electrically connected to the drain region. The interconnect structure can be formed as stacked conductive layers laid out in alternating strips. The conductive plane extends under a gate terminal of the semiconductor device. An insulating layer is formed over the substrate and a field plate is formed in the insulating layer. The field plate is electrically connected the source terminal. A stress relief layer is formed over a surface of the substrate opposite the gate structure.