MOSFET Interfacial Oxide Layer Threshold Voltage Modulation
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Solution Overview
Problem
The production of MOSFETs and CMOSFETs is complicated by the need to form gate electrodes with optimum threshold voltages, leading to increased production costs and efficiency losses.
Innovation Solution
Incorporating third elements, such as Al and Ge, into the interfacial oxide and high-k dielectric layers of MOSFETs, with peak doping densities located below the high-k/interfacial oxide interface, to modulate the threshold voltage through simpler procedures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate electrodes with optimum threshold voltages are formed according to device structure and conductivity types, then device performance is improved, but production process complexity and costs increase
Solution Approach 1:
The patent applies parameter changes by modifying the doping concentration and depth parameters of the interfacial oxide layer to achieve different threshold voltages. By controlling the peak doping concentration (e.g., 1×10^19 to 1×10^21 atoms/cm³) and peak depth (e.g., 0.5 nm to 5 nm below the high-k/interfacial oxide interface), the work function of the gate electrode is adjusted, enabling threshold voltage optimization without adding process steps.
Solution Approach 2:
The patent implements preliminary action by incorporating dopants into the interfacial oxide layer during the gate dielectric formation process, before gate electrode deposition. This preliminary doping establishes the desired threshold voltage characteristics in advance, eliminating the need for subsequent gate electrode modification steps and simplifying the overall production process.
2Manufacturing precision
If conventional doping methods are used to modulate threshold voltage, then threshold voltage control is achieved, but dosing amount and process complexity increase
Solution Approach 1:
The patent applies local quality by concentrating dopants at a specific depth within the interfacial oxide layer rather than uniform distribution. The peak doping concentration is localized at a controlled depth (e.g., 1 nm to 10 nm below the high-k/interfacial oxide interface), creating a localized region that efficiently modulates the work function with minimal total dopant dosage while achieving precise threshold voltage control.
Solution Approach 2:
The patent replaces conventional mechanical doping methods (such as ion implantation requiring high doses) with a chemical vapor deposition-based doping approach. By incorporating dopants during the atomic layer deposition or chemical vapor deposition of the interfacial oxide layer, the process achieves efficient doping with lower dosing amounts and reduced process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for enhanced threshold voltage modulation with improved device performance, reducing the complexity and cost of producing MOSFETs and CMOSFETs by enabling easier work function modulation with less dosing compared to conventional methods.
Implementation Method 1
an interfacial oxide layer (IL) formed on the channel region into which at least one element disparate from Si, O, or N is incorporated at a peak concentration greater than 1×10^19 atoms/cm2
Data Source
AI summary
MOSFETs and methods of making MOSFETs are provided. According to one embodiment, a semiconductor device includes a substrate and a Metal-Oxide-Semiconductor (MOS) transistor that includes a semiconductor region formed on the substrate, a source region and drain region formed in the semiconductor region that are separated from each other, a channel region formed in the semiconductor region that separates the source region and the drain region, an interfacial oxide layer (IL) formed on the channel region into which at least one element disparate from Si, O, or N is incorporated at a peak concentration greater than 1×1019 atoms/cm2, and a high-k dielectric layer formed on the interfacial oxide layer having a high-k/IL interface at a depth substantially adjacent to the IL. In addition, at least one depth of peak density of the incorporated element(s) is located substantially below the high-k/IL interface.