3D MOSFET Isolation Layer Gradient for Reliable Gate Control
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in reliability and electric characteristics.
Innovation Solution
A three-dimensional semiconductor device is designed with a specific structure including active patterns, channel patterns, and a gate electrode, utilizing a device isolation layer with varying silicon concentrations and a multi-layered gate insulating layer to enhance process efficiency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If MOS-FETs are scaled down to reduce pattern size and design rule, then device miniaturization is achieved, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar MOS-FET structure to a three-dimensional structure where the gate electrode wraps around the channel pattern in a vertical configuration. This dimensional change allows continued miniaturization in the lateral plane while maintaining or improving operational properties through enhanced gate control in the vertical dimension.
Solution Approach 2:
The device isolation layer is engineered with a silicon concentration gradient, where the first portion has higher silicon concentration (41-45 at%) than the second portion. This local variation in material composition optimizes the electrical characteristics at specific locations, particularly at the interface with the gate electrode, to compensate for scale-down effects.
2Reliability
If device isolation layer has higher silicon concentration at the interface with gate electrode, then electrical characteristics improve, but manufacturing complexity increases
Solution Approach 1:
The silicon concentration in the device isolation layer is varied as a continuous gradient rather than discrete layers. The concentration transitions from a first value (41-45 at%) at the gate electrode interface to a second lower value deeper in the isolation layer. This parameter change approach simplifies manufacturing compared to creating multiple discrete doped layers while achieving the desired electrical characteristics.
Solution Approach 2:
The device isolation layer is formed with the predetermined silicon concentration gradient before the channel and gate electrode patterns are created. This preliminary structuring of the isolation layer with optimized electrical properties at the interface region simplifies subsequent processing steps and ensures proper electrical characteristics are established early in the fabrication sequence.
Data Source
AI summary
A semiconductor device may include a first active pattern and a second active pattern on a substrate, a device isolation layer in a trench between the first active pattern and the second active pattern, a first channel pattern and a second channel pattern provided on the first active pattern and the second active pattern, respectively, each of the first channel pattern and the second channel pattern including a plurality of stacked semiconductor patterns, and a gate electrode on the first channel pattern and the second channel pattern. The device isolation layer may include a first portion and a second portion which are vertically overlapped with the gate electrode. The first portion may be provided on the second portion. A silicon concentration of the first portion may be higher than a silicon concentration of the second portion.