MOSFET Isolation Structure for Monolithic IC Integration
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Solution Overview
Problem
Conventional MOSFETs with non-isolation structures suffer from noise interference and ground bounce due to uncontrolled transistor current, making them unsuitable for monolithic IC integration, and their isolation structures have complex manufacturing processes and high costs.
Innovation Solution
A MOSFET with an isolation structure formed through a low voltage complementary metal oxide semiconductor (LVCMOS) manufacturing process using a standard well structure, eliminating the need for additional epitaxial layers and masks, which simplifies the fabrication process while achieving high breakdown voltage and low on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional non-isolation transistor structures are used, then manufacturing process is simple, but noise interference and ground bounce occur due to uncontrolled transistor current
Solution Approach 1:
The transistor structure is segmented into isolated regions using P-type diffusion regions that surround the N-type diffusion regions. This segmentation creates electrically isolated transistor units, preventing current from flowing around the substrate and eliminating noise interference and ground bounce while maintaining manufacturing simplicity through integration into the standard LVCMOS process flow.
Solution Approach 2:
P-type diffusion regions are locally introduced around specific N-type diffusion regions to create isolation structures. This local modification provides targeted isolation where needed without requiring global process changes, maintaining overall process simplicity while solving the noise and ground bounce problems in specific locations.
2Object-affected harmful factors
If conventional isolation structures with additional epitaxial layers are used, then transistor isolation is achieved, but manufacturing process becomes complicated and cost increases
Solution Approach 1:
The isolation function is merged with the existing well structure formation process. P-type diffusion regions are formed during the same fabrication steps used to create N-wells and transistors, combining multiple functions into a unified process flow. This eliminates the need for separate isolation processing steps and additional epitaxial layer fabrication, reducing manufacturing complexity while achieving effective transistor isolation.
Solution Approach 2:
The P-type diffusion regions serve multiple functions: they act as isolation structures between transistors, provide local back-bias control, and integrate with the existing well formation process. This multi-functionality eliminates the need for dedicated isolation processing steps, reducing overall manufacturing complexity while achieving comprehensive transistor isolation.
3Object-affected harmful factors
If conventional isolation structures with additional epitaxial layers are used, then transistor isolation is achieved, but fabrication cost increases
Solution Approach 1:
The isolation function is merged with the existing well structure formation process. P-type diffusion regions are formed during the same fabrication steps used to create N-wells and transistors, combining multiple functions into a unified process flow. This eliminates the need for separate isolation processing steps and additional epitaxial layer fabrication, reducing manufacturing complexity while achieving effective transistor isolation.
Solution Approach 2:
The P-type diffusion regions serve multiple functions: they act as isolation structures between transistors, provide local back-bias control, and integrate with the existing well formation process. This multi-functionality eliminates the need for dedicated isolation processing steps, reducing overall manufacturing complexity while achieving comprehensive transistor isolation.
4Ease of manufacture
If standard well structure is used without additional epitaxial layers, then manufacturing cost is reduced, but transistor isolation may be insufficient
Solution Approach 1:
P-type diffusion regions are formed preliminarily during the well structure fabrication process, before final transistor formation. This preliminary action establishes isolation boundaries early in the process, ensuring that subsequent transistor fabrication occurs within properly isolated regions. The preliminary formation of these diffusion regions prevents current leakage and noise interference from the outset, maintaining effective isolation without requiring additional expensive epitaxial layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables monolithic IC integration by providing a cost-effective, high-yield, isolated transistor structure with improved isolation and breakdown voltage, reducing manufacturing complexity and costs.
Implementation Method 1
the first P-type diffusion region surrounds the first source region and the first contact region
Data Source
AI summary
A MOSFET with an isolation structure is provided. An N-type MOSFET includes a first N-type buried layer and a P-type epitaxial layer disposed in a P-type substrate. A P-type FET includes a second N-type buried layer and the P-type epitaxial layer disposed in the P-type substrate. The first, second N-type buried layers and the P-type epitaxial layer provide isolation between FETs. In addition, a plurality of separated P-type regions disposed in the P-type epitaxial layer further provides an isolation effect. A first gap exists between a first thick field oxide layer and a first P-type region, for raising a breakdown voltage of the N-type FET. A second gap exists between a second thick field oxide layer and a second N-well, for raising a breakdown voltage of the P-type FET.