High Voltage Power MOSFET LDD Segmentation for On-Resistance
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Solution Overview
Problem
Conventional high voltage power MOSFETs face a significant challenge in reducing on-resistance while maintaining high reverse breakdown voltage, as the lightly doped drain (LDD) region limits current conductivity due to high resistance, and existing methods are complex to implement or unstable.
Innovation Solution
The solution involves embedding an electrical field in the LDD region using a conducting path with a thin insulating layer, which depletes charge carriers during the off-state to enhance blocking voltage and accumulates charge carriers during the on-state, reducing on-resistance through a resistive layer or serially connected P-N junctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If LDD doping density is increased to reduce on-resistance, then on-resistance decreases, but reverse breakdown voltage decreases
Solution Approach 1:
The LDD region is segmented into multiple lightly doped regions with different doping densities arranged in columns. This segmentation allows each column to contribute differently to the electrical characteristics, enabling the structure to achieve low on-resistance while maintaining high reverse breakdown voltage through the combined effect of multiple regions with optimized doping profiles.
Solution Approach 2:
Different regions within the LDD structure have different doping densities tailored to their specific functional requirements. Regions closer to the channel have higher doping to reduce on-resistance, while regions closer to the drain have lower doping to maintain high breakdown voltage. This local optimization of doping quality resolves the contradiction between low on-resistance and high reverse breakdown voltage.
2Loss of energy
If RESURF or field control methods are used to increase LDD doping, then on-resistance decreases, but device complexity increases
Solution Approach 1:
The patent combines the benefits of RESURF (surface field control) and charge balance effects into a unified multiple LDD structure. By merging these concepts into a single integrated design with columns of P and N type materials, the patent achieves low on-resistance without requiring separate complex control mechanisms, thus reducing overall device complexity while maintaining performance.
3Loss of energy
If charge balance method is used to deplete LDD, then on-resistance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses systematic parameter changes in the doping profiles of the multiple LDD regions to achieve the desired electrical characteristics. By carefully designing the doping densities and spatial distributions in each column, the structure achieves effective LDD depletion and low on-resistance through inherent parameter optimization rather than requiring extremely precise manufacturing control, thus reducing the stringency of manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces on-resistance by increasing carrier density during the on-state and maintaining stability during the off-state, allowing for scalable and technologically advanced semiconductor devices with improved conductivity and voltage blocking capabilities.
Implementation Method 1
The conducting path is separated from the LDD region by a thin layer of insulating dielectric material
Implementation Method 2
During the voltage blocking period, or off-state, a small current flows through the path, being resistors or junction devices, provides a stable potential distribution and embedded electrical field depleting the LDD region of charge carriers
Implementation Method 3
a small current flows through the path, being resistors or junction devices
Implementation Method 4
A control mechanism of embedding structures also allows LDD to be driven into accumulation in on-state, which results in significant on-resistance reduction
Data Source
AI summary
A high voltage power MOSFET includes a semiconductor substrate doped by a first conducting type, a source doped by a second conducting type and over the semiconductor substrate, and a drain region doped by the second conducting type and on the semiconductor substrate. One or more drain layers doped by the second conducting type and on the semiconductor substrate span between the body region and the drain region. An insulating layer is formed on at least a portion of the body region and over the one or more drain layers. A voltage regulating layer on the insulating layer can produce voltage distributions in the one or more drain layers to deplete charge carriers to increase blockage voltage in an off state, and to accumulate charge carriers in an on state to reduce on-state resistance.