MOSFET Level Shifter With Dynamic Impedance for Fast Low-Power Switching
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Solution Overview
Problem
Voltage level-shifters in System-on-Chips (SoCs) face challenges in providing fast transition times with low power consumption as they become bottlenecks due to increased power domains, necessitating improved power-performance trade-offs.
Innovation Solution
A level-shifter design that maintains high impedance at critical switching nodes with positive feedback loops, accelerating output transitions and 're-arming' itself during a predetermined time to ensure readiness for the next switching event, utilizing a combination of n-type and p-type MOSFET transistors and pull-up/pull-down networks to manage voltage levels across different power domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional level-shifter designs are used to convert logic signals between different power domains, then voltage level conversion is achieved, but transition times are slow and power consumption is high
Solution Approach 1:
The patent dynamically adjusts the impedance of pull-up and pull-down networks based on operating conditions. During switching transitions, the circuits maintain low impedance to enable fast transitions, while during idle periods they switch to high impedance to minimize power consumption. This dynamic adaptation resolves the contradiction between fast transition times and low power consumption.
Solution Approach 2:
The invention changes the electrical parameters (impedance values) of the pull-up and pull-down networks depending on the operational state. By varying the impedance parameter from low during transitions to high during idle periods, the circuit achieves both fast switching when needed and low power consumption during steady states, resolving the speed-power tradeoff.
2Speed
If high impedance is maintained at critical switching nodes to accelerate output transitions, then transition speed improves, but power consumption increases during active periods
Solution Approach 1:
The patent employs periodic switching of the pull-up and pull-down networks between high-impedance and low-impedance states. The high-impedance state is activated only during the brief periods when transitions are needed, while the low-impedance state is maintained during idle periods to minimize power loss. This periodic action allows the circuit to achieve fast transitions when required while minimizing energy loss during steady operation.
Solution Approach 2:
The circuit prepares the pull-up and pull-down networks in advance by maintaining them in a high-impedance ready state during idle periods, so that when a transition is required, they can quickly switch to low impedance to accelerate the transition. This preliminary preparation enables fast transitions without sustained high power consumption.
Data Source
AI summary
An integrated circuit device includes a level shifter circuit with a supply voltage rail to provide a supply voltage, a first pull-up circuit coupled between the supply voltage rail and a first node, a second pull-up circuit coupled between the supply voltage rail and a second node, a first switch including a first terminal coupled to the supply voltage rail, a second terminal coupled to the first node, and a control terminal coupled to the second node, and an inverter including an input terminal coupled to the first node, a voltage supply terminal coupled to the supply voltage, and an output terminal to provide an output voltage from the level shifter circuit.