Differential Line Driver Output Stage for Low-Reflection Switching

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Solution Overview

Problem

Existing differential circuit arrangements for high data rate transmission suffer from low power efficiency and increased output impedance during switching phases, leading to signal quality degradation and reflection issues.

Innovation Solution

A circuit arrangement with controlled output impedance is implemented, utilizing n-channel MOSFETs and resistors to maintain consistent output impedance during switching phases, reducing shoot-through currents and optimizing resistor values to achieve high signal quality and low reflection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If differential circuit arrangements are used for high data rate transmission, then interference is minimized, but power efficiency is low

Engineering Contradiction:
Improvesignal qualityVSAvoidpower efficiency
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the impedance parameter dynamically during switching phases by introducing series resistors that are connected in specific configurations. These resistors modify the output impedance characteristics during transitions, allowing the circuit to maintain better signal quality while reducing the current draw during critical switching periods, thereby improving power efficiency.

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If simple inverter circuits are used for low data rate transmission, then power efficiency is improved, but signal reflections are not suppressed

Engineering Contradiction:
Improvepower efficiencyVSAvoidsignal quality
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent introduces dynamic impedance control by using switching elements that adjust the output impedance based on the operating phase. During switching transitions, the impedance is dynamically adjusted to match the line impedance, preventing reflections. This dynamic adaptation allows the simple inverter structure to maintain signal quality comparable to complex differential circuits while retaining power efficiency.

Inventive Principle:
Principle #15Dynamics

3Reliability

If impedance matching is implemented for high data rates, then signal reflections are absorbed, but device complexity increases

Engineering Contradiction:
Improvesignal qualityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent designs the output stage to serve multiple functions: it acts as a simple inverter during steady-state operation for power efficiency, and simultaneously provides impedance matching during switching phases through the strategically placed series resistors. This multi-functionality allows a single circuit configuration to handle both low-complexity operation and high-quality signal transmission without requiring separate dedicated circuits for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP2177000B1Circuit arrangement and method for driving at least one differential line
Publication Date: 2014.04.16 SILICON LINE
  • EP2177000B1 patent drawingFigure 1A
  • EP2177000B1 patent drawingFigure 1B
  • EP2177000B1 patent drawingFigure 1C

AI summary

In the case of a circuit arrangement (S; S'; S'; S''), particularly a driver output stage, which can be powered by means of at least one voltage sources (SQ), for driving at least one differential line which can be connected - to at least one first output connection (Out +) and also - to at least one second output connection (Out -) for the purpose of, particularly digital, data transmission, wherein the circuit arrangement (S; S'; S'; S'') has at least two paths (P1, P2), which are arranged in mirror-image fashion relative to one another and which connect the voltage source (SQ) to at least one reference potential (GND), particularly earth potential or ground potential or zero potential, and also in the case of a method for driving at least one differential line using at least one such circuit arrangement (S; S'; S'; S''), an increased output impedance (ZOut1, ZOut2) is avoided during the switching phase and this ensures high signal quality.