N-type MOSFET Metal Gate Work Function Tuning
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Solution Overview
Problem
The combination of a metal gate and high-K gate dielectric layer in MOSFETs faces challenges such as thermal stability and interface state issues, making it difficult to achieve a properly low threshold voltage due to the Fermi pinning effect, and existing methods struggle to adjust the effective work function effectively.
Innovation Solution
A method for manufacturing an N-type MOSFET that involves forming a high-K gate dielectric layer, implanting dopant ions into a metal gate layer, and performing annealing to diffuse these ions and generate electric dipoles at specific interfaces, allowing for adjustment of the effective work function by altering the metal gate characteristics and forming suitable electric dipoles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal gate and high-K gate dielectric layer are combined in MOSFET, then gate resistance is reduced and boron penetration is avoided, but thermal stability and interface state problems occur, making it difficult to achieve proper threshold voltage
Solution Approach 1:
An interface oxide layer is introduced as an intermediary between the semiconductor substrate and the high-K gate dielectric layer. This intermediate layer improves thermal stability and reduces interface state density, resolving the contradiction between device reliability and thermal stability while enabling proper threshold voltage control in metal gate MOSFETs.
2Reliability
If a metal gate and high-K gate dielectric layer are combined in MOSFET, then gate resistance is reduced and boron penetration is avoided, but interface state problems occur
Solution Approach 1:
The interface oxide layer serves as a mediator between the semiconductor substrate and high-K gate dielectric, reducing interface state density and improving device reliability by eliminating direct contact between incompatible materials.
3Ease of manufacture
If material selection alone is used to achieve low effective work function, then simplicity is maintained, but it is difficult to achieve the desired low threshold voltage
Solution Approach 1:
The effective work function is adjusted by changing physical and chemical parameters through dopant ion implantation and annealing processes, which modify the metal gate layer characteristics and create electric dipoles at interfaces, enabling precise threshold voltage control beyond what material selection alone can achieve.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables stable and high-performance semiconductor devices with adjustable effective work functions, improving the reliability and threshold voltage control of MOSFETs by altering the metal gate characteristics and forming electric dipoles at the high-K gate dielectric interfaces.
Implementation Method 1
performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer
Implementation Method 2
generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer
Data Source
AI summary
The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.