MOSFET Nanowire Channel Fabrication via Self-Aligned Etching
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Solution Overview
Problem
The challenge in very large scale integration of MOSFETs is the short channel effect, which limits the integration and reliability of silicon-based transistors, and the complexity of fabricating MOSFETs with nanowire structures.
Innovation Solution
A self-aligning method for fabricating MOSFETs with multiple channels using a sequence of material layers and mask patterns to form recess regions, etch openings, and implant impurity ions, allowing for the formation of nanowire-shaped channel regions without the need for doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length of MOSFET is scaled down to improve integration, then the integration density increases, but the short channel effect worsens causing threshold voltage reduction and reliability degradation
Solution Approach 1:
The patent transitions from planar 2D channel structure to three-dimensional nanowire channel structure. The nanowire channel extends vertically from the substrate, creating a new dimensional approach that enhances gate control over the channel while maintaining compact footprint, thereby improving integration density without suffering from short channel effects
Solution Approach 2:
The gate electrode is positioned to completely surround the nanowire channel in a nested configuration, with the gate wrapping around the channel from multiple sides. This nested arrangement maximizes the gate's electrostatic control over the channel, maintaining threshold voltage stability even as channel dimensions are reduced for higher integration
2Reliability
If single crystal silicon is used to maintain material quality, then device reliability is improved, but the channel area resistance increases and integration is limited
Solution Approach 1:
The patent changes the geometric parameters of the channel from planar to vertical nanowire structure, and modifies the doping parameters by forming lightly doped drain regions with specific concentration gradients. These parameter changes reduce channel resistance while maintaining the high material quality of single crystal silicon, enabling better control over electrical characteristics
3Manufacturing precision
If nanowire structure is adopted to improve electrical conductivity and reduce channel resistance, then device performance is enhanced, but the fabrication complexity increases significantly
Solution Approach 1:
The patent performs preliminary actions by pre-forming sacrificial oxide layers and placeholder structures before creating the final nanowire channel. The selective oxidation and removal processes are planned in advance, allowing the nanowire structure to be formed through controlled material addition and removal rather than attempting to directly pattern the complex three-dimensional channel geometry
Solution Approach 2:
The patent uses intermediary materials such as sacrificial oxide layers and placeholder structures that facilitate the formation of the nanowire channel. These intermediary elements are temporarily introduced to enable subsequent processing steps, then selectively removed to reveal the final nanowire structure, thereby simplifying the overall fabrication process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the efficient fabrication of MOSFETs with nanowire channels, improving electrical conductivity and reducing channel resistance, while maintaining high integration and reliability, and effectively addressing the short channel effect.
Implementation Method 1
a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer
Implementation Method 2
impurity ions are implanted using the gate electrode layer as an ion-implantation mask to form a first ion-implanted region on the semiconductor layer
Implementation Method 3
A first mask layer pattern extending in a first direction and having a predetermined width is formed on the semiconductor layer, and the semiconductor layer and the first material layer are etched using the first mask layer pattern as an etch mask
Data Source
AI summary
A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.