MOSFET Channel Structure With Nested P-Wells for Lower Resistance
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Solution Overview
Problem
Existing Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) face challenges in efficiently forming structures that enhance channel density and reduce resistance, particularly in the formation of P-well and N-source portions within a drift layer.
Innovation Solution
The proposed solution involves a field effect transistor design that includes a drift layer with integral P-well and N-source portions, where the P-well portions have sidewalls forming an enclosed structure, and the N-source portions surround the outer perimeter of these sidewalls. This design also features an upwardly extending intermediate portion of the drift layer through the inner perimeter of the P-well sidewalls, creating additional channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MOSFET structures are used, then manufacturing is simpler, but channel density and conductivity are insufficient
Solution Approach 1:
The patent implements nested structures where N-source portions are positioned within P-well portions, which are themselves within the drift layer. The P-well sidewalls form enclosed structures that contain the N-source regions, creating a nested arrangement that increases channel density while maintaining manufacturing feasibility through sequential formation processes.
Solution Approach 2:
The patent transitions from planar channel structures to three-dimensional channel regions by forming P-well portions with upwardly extending sidewalls that enclose N-source portions. This vertical dimensionality increase creates multiple channel paths within the same footprint, thereby increasing channel density and electrical conductivity without proportionally increasing device area.
2Reliability
If channel density is increased through complex structures, then conductivity improves, but manufacturing difficulty increases
Solution Approach 1:
The patent forms the P-well portions and their sidewall structures before introducing the N-source portions. This preliminary formation of the P-well enclosed structures provides defined regions that guide subsequent N-source doping or deposition, simplifying the manufacturing process by establishing a template that reduces alignment complexity and process steps.
Solution Approach 2:
The patent divides the channel region into multiple discrete N-source portions, each enclosed by P-well sidewalls. This segmentation creates independent channel regions that can be formed through separate doping or deposition steps, allowing for better process control and reduced complexity compared to forming a single complex continuous structure.
3Reliability
If conventional P-well and N-source structures are used, then manufacturing is easier, but resistance remains high
Solution Approach 1:
The N-source portions are nested within the P-well portions, with the P-well sidewalls forming enclosed structures that contain the N-source regions. This nested configuration reduces the effective distance between source and channel regions, thereby reducing resistance while maintaining a manageable structural complexity through standard semiconductor fabrication techniques.
Data Source
AI summary
A field effect transistor includes first section and second sections. The first section includes a drift layer. A first P-well is disposed over the drift layer. A first N-source is disposed over the first P-well. A first channel is disposed in an upper portion of the first P-well. The second section includes an area P-well disposed within the drift layer and formed integral with the first P-well. The area P-well includes sidewalls that extend upwards from the drift layer to form an enclosed structure with an outer perimeter and an inner perimeter. An area N-source surrounds the outer perimeter and is formed integral with the first N-source. An upwardly extending intermediate portion of the drift layer extends upwards though the inner perimeter. A second channel is disposed in an upper portion of the sidewalls and is bounded by the inner perimeter and outer perimeter of the sidewalls.