Trench Gate Vertical MOSFET Noise Reduction via Source-Drain Capacitance
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing noise effects without increasing chip area or complicating processes, particularly in trench gate type vertical MOSFETs, where low-frequency noise is difficult to pass through junction capacitance due to high impedance.
Innovation Solution
A semiconductor device configuration that includes a semiconductor substrate with a drain region, drift region, base region, and source region, along with a conductive layer and interlayer insulating films, where the conductive layer is formed by thermal oxidation and electrically coupled to the drain region, forming a source-drain capacitance without increasing chip area or complicating processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If additional capacitance is formed outside the trench MOS region, then noise effects are reduced, but chip area increases
Solution Approach 1:
The patent merges the capacitance-forming structure with the existing trench gate structure by forming the conductive layer within the same trench that contains the gate electrode. This integration allows the capacitance structure to share the same physical space as the gate structure, reducing noise effects without increasing chip area.
Solution Approach 2:
The patent utilizes the vertical dimension within the trench structure to form the capacitance. By positioning the conductive layer at a different depth within the same trench (closer to the second surface than the gate electrode), the design creates capacitance in the vertical dimension rather than requiring additional horizontal space.
2Object-affected harmful factors
If trench is formed deeper and insulating film is formed repeatedly, then source-drain capacitance is formed, but processes become complicated
Solution Approach 1:
The patent makes the trench structure multi-functional by using the same trench to accommodate both the gate electrode and the capacitance-forming conductive layer. The insulating film within the trench serves dual purposes: insulating the gate electrode and providing the dielectric medium for the capacitance structure, thereby reducing the need for separate processing steps.
Solution Approach 2:
The patent forms the insulating film and conductive layer in a sequence that leverages previous processing steps. The insulating film is formed first within the trench, followed by the conductive layer, allowing each step to build upon the previous one rather than requiring independent formation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces noise effects without increasing chip area or complicating processes, by forming source-drain capacitance through thermal oxidation of the conductive layer, ensuring high insulating resistance and accurate capacitance control.
Implementation Method 1
The conductive layer is formed of a conductor which changes into an insulator when being oxidized
Data Source
AI summary
The present invention provides a semiconductor device that can reduce effects of noise without complicating processes or increasing chip area. The semiconductor device according to an aspect of the present invention includes a semiconductor substrate, a drain region, a drift region, a base region, a source region, a gate electrode, an interlayer insulating film, a conductive layer electrically coupled to the drain region, a wiring line, and a contact plug electrically coupled to the source region and the wiring line. The interlayer insulating film has an intermediate interlayer insulating film. The intermediate interlayer insulating film is arranged between the conductive layer and the contact plug. The intermediate interlayer insulating film is a thermal oxide film of a material that forms the conductive layer.