MOSFET Noise Testing via 3D Shielding and Deep Well Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current MOSFET noise testing methods require high accuracy and expensive shielding to isolate devices from external interference, leading to unstable and erroneous results due to the inability to completely eliminate outside noise.
Innovation Solution
A semiconductor test structure featuring a MOSFET device with a metal shielding layer and deep well regions connected via vertical vias to ground, forming a three-dimensional shield structure that completely isolates the device from external noise during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional shield space is established to reduce noise, then noise isolation is improved, but cost increases and complete isolation cannot be achieved
Solution Approach 1:
The patent transitions from conventional planar shielding to a three-dimensional shielding structure by forming deep well regions extending vertically into the semiconductor substrate and connecting them to the metal shielding layer through vertical vias. This vertical dimensionality enhancement creates a comprehensive noise isolation barrier that completely surrounds the MOSFET device, achieving effective noise isolation while avoiding the high costs associated with conventional shield spaces.
2Object-affected harmful factors
If conventional shield space is established to reduce noise, then noise isolation is improved, but the shielding structure becomes complex and expensive
Solution Approach 1:
The shielding structure is segmented into distinct functional components: a metal shielding layer formed on the MOSFET device, deep well regions formed in the semiconductor substrate, and vertical vias connecting them. This segmentation allows each component to be formed using standard semiconductor fabrication processes, simplifying the overall structure while achieving complete noise isolation.
Solution Approach 2:
The patent introduces vertical depth as an additional dimension to the shielding structure. Deep well regions extend vertically into the substrate, and vertical vias provide conductive paths through the substrate thickness. This three-dimensional configuration achieves complete noise isolation without requiring complex lateral shielding structures.
3Measurement precision
If wafer level device noise test is performed with high accuracy requirements, then measurement precision is improved, but test stability deteriorates due to external noise interference
Solution Approach 1:
The shielding structure is built into the semiconductor device itself before testing, with the metal shielding layer and deep well regions pre-configured to block external noise. This preliminary protective action ensures that when noise measurements are taken, the device is already isolated from external interference, maintaining both measurement precision and test stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for accurate MOSFET noise testing by effectively isolating the device from external interference, providing reliable and precise noise measurement results without the need for expensive shielding.
Implementation Method 1
a metal shielding layer formed on the MOSFET device, the metal shielding layer completely covering the MOSFET device
Implementation Method 2
a vertical via is formed between the portion of the metal shielding layer extending beyond the first well region and the portion of the deep well region extending beyond the first well region to couple the metal shielding layer to the deep well region
Data Source
AI summary
The present invention provides a semiconductor test structure for MOSFET noise testing. The semiconductor test structure includes: a MOSFET device having a first conductivity type formed on a first well region of a semiconductor substrate; a metal shielding layer formed on the MOSFET device, the metal shielding layer completely covering the MOSFET device and extending beyond the circumference of the first well region; a deep well region having a second conductivity type formed in the semiconductor substrate close to the bottom surface of the first well region, the deep well region extending beyond the circumference of the first well region; wherein a vertical via is formed between the portion of the metal shielding layer extending beyond the first well region and the portion of the deep well region extending beyond the first well region to couple the metal shielding layer to the deep well region. The metal shielding layer is used to be connected to the ground terminal of a testing machine during testing, and the first conductivity type and the second conductivity type are opposite conductivity types.