MOSFET Offset Layer Impurity Profile for Snap-Back Voltage
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Solution Overview
Problem
High voltage MOSFETs with shallow trench isolation (STI) structures experience snap-back voltage issues due to the location of the impurity concentration profile peak, leading to reduced performance in high withstand voltage applications.
Innovation Solution
The semiconductor device features a body layer and an offset layer with a peak impurity concentration profile positioned deeper than the insulating film, enhancing the snap-back voltage by reducing resistance and current density at the edge of the trench, and maintaining a uniform electric field.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If shallow trench isolation (STI) is used for element separation in high voltage MOSFETs, then manufacturing precision and miniaturization are improved, but snap-back voltage occurs at about 15V when gate is on
Solution Approach 1:
The patent applies local quality by creating a specific impurity concentration distribution in the offset layer, with a peak positioned at a depth between 0.5-2.0 μm from the surface. This localized impurity peak modifies the electrical properties specifically in the offset layer region, improving snap-back voltage characteristics without affecting other structural elements. The selective placement of impurities addresses the snap-back issue locally while maintaining the overall STI structure.
Solution Approach 2:
The patent changes the impurity concentration parameter in the offset layer by forming a peak at a specific depth range (0.5-2.0 μm from surface) with controlled concentration levels. This parameter modification in the offset layer's impurity profile alters the electric field distribution and carrier behavior, thereby suppressing snap-back voltage while preserving the manufacturing advantages of STI isolation.
2Ease of manufacture
If impurity concentration peak is positioned shallow in the offset layer, then manufacturing is simplified, but current concentration occurs at trench edges leading to reduced snap-back voltage
Solution Approach 1:
The patent moves the impurity concentration peak from the shallow horizontal plane to a deeper vertical dimension, positioning it at 0.5-2.0 μm depth from the surface. This dimensional transition in impurity placement reduces current concentration at trench edges by distributing the electric field more uniformly in the vertical direction, thereby improving snap-back voltage while maintaining manufacturability through controlled implantation or diffusion processes.
3Productivity
If STI structure is used for miniaturization, then device density is improved, but impact ionization increases at trench edges reducing high voltage handling capability
Solution Approach 1:
The patent applies local quality by introducing a controlled impurity peak specifically in the offset layer at a depth of 0.5-2.0 μm, which locally modifies the electric field distribution. This localized impurity region reduces impact ionization at trench edges by smoothing the electric field gradient, thereby suppressing harmful effects while maintaining the high device density enabled by STI miniaturization.
Solution Approach 2:
The patent converts the potentially harmful effect of trench edge electric field concentration into a benefit by strategically placing impurities to create a smoothing effect. The impurity peak in the offset layer transforms the sharp electric field gradient at trench edges into a more uniform distribution, reducing impact ionization and converting what would be a harmful concentration effect into a beneficial field-modification mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively increases the snap-back voltage during on-operation by reducing current concentration at the trench edges and suppressing impact ionization, resulting in improved high voltage handling capabilities.
Implementation Method 1
suppressing impact ionization
Data Source
AI summary
A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.