MOSFET Packaging Structure With Short Interconnects for Low Inductance
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Solution Overview
Problem
The independently packaged gallium nitride MOSFET and driver occupy a large volume and require a large quantity of leads, introducing parasitic inductance and leading to switching losses, which is not conducive to miniaturization and high-frequency driving.
Innovation Solution
A MOSFET packaging structure with a carrier chip, MOSFET chip, and conductive members, where the MOSFET chip is mounted on the carrier chip with short interconnect distances and conductive members connected to input, output, and ground gaskets, reducing parasitic inductance and enhancing thermal conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If independently packaged gallium nitride MOSFET and driver are used, then device functionality is achieved, but volume occupation increases and parasitic inductance is introduced
Solution Approach 1:
The patent merges the MOSFET chip, driver chip, and heat dissipation substrate into a single integrated packaging structure. The MOSFET chip and driver chip are mounted on the same heat dissipation substrate with direct electrical connections, eliminating the need for separate packages and reducing overall volume while maintaining full device functionality.
Solution Approach 2:
The patent employs a nested arrangement where the driver chip is positioned adjacent to the MOSFET chip on the heat dissipation substrate, with both chips sharing the same packaging footprint. The electrical connections are routed through the substrate itself, nesting multiple functions within a compact three-dimensional layout that minimizes volume occupation.
2Reliability
If a large quantity of leads are used to implement electrical connection, then electrical connectivity is achieved, but parasitic inductance increases leading to switching loss
Solution Approach 1:
The patent extracts the electrical connection function from traditional wire leads and implements it through direct metallurgical bonds and substrate-integrated traces. The electrical connections are made through bonding wires or tabs that directly connect the MOSFET chip electrodes to the driver chip and heat dissipation substrate, eliminating long lead paths and associated parasitic inductance.
Solution Approach 2:
The heat dissipation substrate serves as an intermediary that provides both thermal management and electrical connection functions. The substrate contains embedded conductive traces and connection points that facilitate low-inductance electrical pathways between the MOSFET chip, driver chip, and external circuitry, while simultaneously conducting heat away from both chips.
3Loss of energy
If short interconnect distance is implemented, then parasitic inductance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary positioning and electrical connection of the MOSFET chip and driver chip to the heat dissipation substrate before final packaging encapsulation. The substrate is pre-prepared with connection traces and mounting areas, allowing for precise alignment and direct bonding operations that achieve short interconnect distances while maintaining manufacturing efficiency through standardized assembly procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure achieves high current carrying capacity, low thermal resistance, and effective heat dissipation, facilitating miniaturization and high-frequency driving while reducing switching losses.
Implementation Method 1
The MOSFET chip generates less heat, and the conductive members have strong thermal conductivity, so that heat dissipation performance of the MOSFET chip can be effectively improved
Implementation Method 2
The conductive members not only have a high current carrying capacity, but also can reduce resistance of the interconnection
Data Source
AI summary
This application provides a MOSFET packaging structure and a manufacturing method thereof, a circuit board assembly, and an electronic device. In the MOSFET packaging structure, a MOSFET chip is mounted on a carrier chip. An interconnect distance between the MOSFET chip and the carrier chip is short and a parasitic inductance is small, making it easy to implement high-frequency driving. In addition, three conductive members are mounted on a second surface of the MOSFET chip to electrically connect to an input gasket, an output gasket, and a ground gasket of the MOSFET chip respectively.