MOSFET Gate and Well Modifications for Parasitic Capacitance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices face limitations in increasing breakdown voltage without incurring additional fabrication costs or reducing the frequency response, as existing techniques often require complex processes and additional steps.
Innovation Solution
The development of a metal oxide semiconductor field effect transistor (MOSFET) structure with a modified gate region and silicide configuration that reduces parasitic capacitance, allowing for a higher breakdown voltage while maintaining improved frequency response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional techniques (separate high voltage process, double diffused drain, extended drain, or cascading transistors) are used to increase breakdown voltage, then the breakdown voltage increases, but the fabrication cost increases due to additional process steps and substrate masking
Solution Approach 1:
The patent combines the high voltage device and standard CMOS devices into a single integrated structure fabricated using the same standard CMOS process. The n-well region serves dual purposes: as the drain extension for the high voltage device and as the substrate for standard CMOS devices, eliminating the need for separate high voltage process steps and reducing fabrication complexity
Solution Approach 2:
The n-well region performs multiple functions simultaneously: it acts as the drain extension region for the high voltage n-channel MOSFET, provides the substrate for standard CMOS devices, and forms part of the isolation structure. This multi-functionality reduces the number of required process steps and masks
2Reliability
If conventional techniques are used to increase breakdown voltage, then the breakdown voltage increases, but the device complexity increases due to additional process steps
Solution Approach 1:
The patent merges the high voltage device fabrication with standard CMOS fabrication processes. The same n-well formation step creates both the high voltage device structure and the substrate for standard devices, reducing the total number of process steps and simplifying the fabrication flow
Solution Approach 2:
The device is segmented into distinct functional regions (high voltage device region with n-well drain extension, standard CMOS region) that can be independently designed but are fabricated using the same process steps, allowing complex functionality to be achieved without proportionally increasing process complexity
3Power
If the operating voltage is increased above breakdown voltage, then the power handling capability increases, but the transistor lifetime decreases due to uncontrollable current increase
Solution Approach 1:
The patent changes the physical parameters of the drain region by extending it into the n-well, which modifies the electric field distribution and breakdown characteristics. This allows the device to operate at higher voltages while maintaining controlled breakdown behavior through the extended drain structure
Data Source
AI summary
An apparatus is disclosed to increase a reduced a parasitic capacitance of a semiconductor device. The semiconductor device includes a modified gate region to effectively reduce an overlap capacitance and modified well regions to effectively reduce a junction capacitance. The modified gate region includes a doped region and an undoped to decrease an effective area of the overlap capacitance. The modified well regions are separated by a substantially horizontal distance to increase an effective distance of the junction capacitance. This decrease in the effective area of the overlap capacitance and this increase in the effective distance of the junction capacitance reduces the parasitic capacitance of the semiconductor device.