Power MOSFET Polyoxide Passivation for Lower Drain Leakage
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Solution Overview
Problem
Power MOSFET devices experience unacceptable increases in drain current leakage due to high interface charge density, which disrupts the electric field and increases drain current at near body-drain breakdown voltage, necessitating a solution to reduce this leakage.
Innovation Solution
The implementation of a stack of ozone-assisted sub-atmospheric pressure thermal chemical vapor deposition (O3 SACVD) TEOS layers, separated by a dielectric region, and thermal annealing to outgas passivation atoms that migrate to interface charges within the polyoxide region, reducing un-oxidized dopant ion-induced interface charge density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MOSFET fabrication processes are used, then manufacturing simplicity is maintained, but drain current leakage increases due to high interface charge density
Solution Approach 1:
The patent segments the gate structure into multiple components: a polysilicon gate electrode, a polyoxide region with un-oxidized dopant ions, and multiple TEOS layers with a dielectric region in between. This segmentation allows each component to serve a specific function in managing interface charge density, thereby reducing drain current leakage without requiring complete redesign of the entire fabrication process
Solution Approach 2:
The patent introduces a dielectric region as an intermediary between the first and second TEOS layers. This dielectric region facilitates the outgassing and migration of passivation atoms to interface charges, acting as a mediator that enables the reduction of interface charge density while maintaining structural integrity during thermal annealing
2Reliability
If interface charge density is reduced through thermal annealing, then drain current leakage decreases, but manufacturing process steps increase
Solution Approach 1:
The patent incorporates TEOS layers and a dielectric region into the fabrication process before final thermal annealing. This preliminary action ensures that passivation atoms are already positioned and structured to effectively migrate to interface charges during the annealing step, maximizing the leakage reduction benefit while minimizing additional process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces interface charge density, leading to a significant decrease in drain current leakage, with a 2.5 times reduction in leakage level compared to previous designs, as demonstrated by the drain current IDSS versus breakdown voltage graph.
Implementation Method 1
thermal annealing to outgas passivation atoms that migrate to interface charges within the polyoxide region
Implementation Method 2
thermal annealing to outgas passivation atoms that migrate to interface charges
Implementation Method 3
ozone-assisted sub-atmospheric pressure thermal chemical vapor deposition (O3 SACVD) TEOS layers
Implementation Method 4
polyoxide region, reducing un-oxidized dopant ion-induced interface charge density
Data Source
AI summary
An integrated circuit includes a polysilicon region that is doped with a dopant. A portion of the polysilicon region is converted to a polyoxide region which includes un-oxidized dopant ions. A stack of layers overlies over the polyoxide region. The stack of layers includes: a first ozone-assisted sub-atmospheric pressure thermal chemical vapor deposition (O3 SACVD) TEOS layer; and a second O3 SACVD TEOS layer; wherein the first and second O3 SACVD TEOS layers are separated from each other by a dielectric region. A thermally annealing is performed at a temperature which induces outgassing of passivation atoms from the first and second O3 SACVD TEOS layers to migrate to passivate interface charges due to the presence of un-oxidized dopant ions in the polyoxide region.