High-Voltage MOSFET Polysilicon Capping Layer Ion Implantation Masking
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Solution Overview
Problem
The fabrication of high-voltage MOSFETs in integrated circuits often results in degraded device performance due to insufficient polysilicon masking layers, which allow dopant ions to penetrate the channel region, especially in smaller scale devices where proximity to logic devices and memory arrays increases the risk of ion implantation interference.
Innovation Solution
The method involves forming additional polysilicon or silicon oxide capping layers over the channel region of high-voltage MOSFETs to provide enhanced masking protection during the lightly-doped drain ion implantation step, using a combination of chemical vapor deposition and etching processes to ensure the masking layers' thickness and coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the polysilicon masking layer thickness is reduced to enable smaller scale devices, then device scaling is achieved, but the masking layer becomes insufficient to block ion implantation into the channel region
Solution Approach 1:
The patent divides the single polysilicon masking layer into multiple separate polysilicon layers deposited at different stages of the fabrication process. The first polysilicon layer is deposited before ion implantation to provide initial masking, and a second polysilicon layer is deposited after ion implantation to restore the gate structure. This segmentation allows each layer to be optimized for its specific function while collectively providing sufficient masking protection even when individual layers are thin.
Solution Approach 2:
The first polysilicon layer is deposited in advance before the ion implantation step to provide masking protection. This preliminary action ensures that the channel region is protected from dopant ion implantation before the harmful process occurs, allowing thin layers to be used without compromising protection effectiveness.
2Reliability
If multiple polysilicon layers are deposited to enhance masking protection, then ion implantation blocking is improved, but fabrication process complexity increases
Solution Approach 1:
The patent combines the masking function and gate structure formation into a single integrated process flow. The first polysilicon layer serves dual purposes as both a masking layer and part of the final gate structure, while the second polysilicon layer restores the gate after ion implantation. This merging eliminates the need for separate masking layers and reduces overall process complexity.
Solution Approach 2:
The first polysilicon layer is temporarily used as a masking layer during ion implantation and then removed (discarded) after serving its protective function. The second polysilicon layer is then deposited to recover and restore the gate structure. This approach allows the use of thin polysilicon layers for masking without permanently increasing the device structure complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents dopant ion implantation into the channel region, maintaining device performance by providing increased protection against ion implantation, even in densely packed integrated circuit designs.
Implementation Method 1
forming a first silicon material layer over a semiconductor substrate
Implementation Method 2
exposing the semiconductor substrate to a dopant ion implantation process
Data Source
AI summary
Methods for fabricating integrated circuits are disclosed. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a silicon material layer over a semiconductor substrate. The method further includes forming a capping layer over the silicon material layer and over the memory gate stack, removing the capping layer from over the memory array region and the high-voltage MOSFET region, forming a second silicon material layer over the capping layer and over the first silicon material layer, and removing the second silicon material layer. The method further includes removing the capping layer from over the first silicon material layer in the logic device region and removing the first and second silicon material layers from the high-voltage MOSFET region. Still further, the method includes forming a photoresist material layer over the memory array region and the logic device region and exposing the semiconductor substrate to an ion implantation process.