MOSFET Power Density Scaling via Voltage and Current Adjustment
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Solution Overview
Problem
As silicon CMOS device dimensions shrink, the rapid drop in power supply voltage levels leads to increased power density, causing reliability issues and heat dissipation problems, making it challenging to maintain constant power density in integrated circuits.
Innovation Solution
The method involves computing settable scaling factors for integrated circuits based on fixed scaling factors from a reference fabrication process, allowing for adjustments in power supply voltage levels and drive current per device width to maintain constant power density, which is achieved by scaling the power supply voltage level and drive current per device width in a manner that keeps power density constant as device dimensions decrease.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are shrunk to increase integration density, then productivity and device density improve, but power density increases dramatically causing heat dissipation problems
Solution Approach 1:
The patent applies parameter changes by systematically adjusting multiple fabrication and circuit parameters across different scaling nodes. Fixed parameters (oxide thickness, well depth, doping concentrations) are scaled according to established relationships, while settable parameters (channel width, gate length, threshold voltage) are optimized to maintain constant power density. This coordinated parameter adjustment enables continued device scaling while controlling power density through precise manipulation of electrical and physical properties.
Solution Approach 2:
The patent implements dynamics by introducing adaptive scaling factors that can be adjusted based on specific application requirements and thermal constraints. The settable scaling factors allow the design to dynamically adapt to different power density targets, enabling the same fabrication process to serve multiple applications with different power requirements while maintaining optimal performance.
2Power
If power supply voltage levels are reduced to maintain constant power density, then power density is controlled, but reliability and noise margins deteriorate
Solution Approach 1:
The patent resolves this contradiction through coordinated parameter changes that decouple voltage scaling from power density control. By adjusting channel dimensions, doping profiles, and threshold voltages in conjunction with supply voltage changes, the patent maintains adequate noise margins and reliability even at reduced voltages. The fixed scaling relationships for critical dimensions ensure that voltage scaling does not compromise device robustness.
Solution Approach 2:
The patent applies local quality by optimizing different regions of the device structure for different functions. The channel region is engineered with specific doping profiles and geometries to maintain carrier mobility and threshold voltage control, while the gate and source/drain regions are optimized for switching performance and reliability. This localized optimization allows voltage scaling without sacrificing noise margins.
3Speed
If drive current per device width is increased to maintain performance, then speed improves, but power density increases
Solution Approach 1:
The patent resolves this contradiction through parameter changes that separate current density optimization from power density control. By adjusting channel width, effective gate length, and threshold voltage independently through the scaling framework, the patent achieves high drive current for fast switching while controlling overall power density through the coordinated scaling of all device parameters. The fixed scaling relationships ensure that current increases are balanced by corresponding changes in other parameters.
Data Source
AI summary
A method for constant power density scaling in MOSFETs is provided. A method for manufacturing an integrated circuit includes computing fixed scaling factors for a first fabrication process based on a second fabrication process, computing settable scaling factors for the integrated circuit to be fabricated using the first fabrication process, determining parameters of the integrated circuit based on the settable scaling factors, and manufacturing the integrated circuit using the determined parameters. The first fabrication process creates devices having a smaller device dimension than the second fabrication process and the settable scaling factors are set based on the fixed scaling factors.