MOSFET-SBD Package Layout for Accurate Thermal Resistance Measurement
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Solution Overview
Problem
The thermal interference between MOSFET and SBD chips in semiconductor devices complicates thermal resistance measurements, making it difficult to design thermal management systems effectively.
Innovation Solution
The semiconductor device design separates MOSFET and SBD chips onto different conductive patterns on an insulating substrate, preventing direct electrical connections between their terminals, allowing for individual thermal resistance measurements and reducing thermal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If MOSFET and SBD chips are mounted on the same die pad, then device integration is improved, but thermal interference between chips increases making thermal resistance measurement difficult
Solution Approach 1:
The patent divides the device into separate functional regions by mounting MOSFET and SBD chips on different die pads, which are electrically isolated from each other. This segmentation allows independent thermal resistance measurement for each chip type while maintaining device integration through separate mounting structures.
Solution Approach 2:
The patent extracts the thermal measurement function by separating the measurement circuits for MOSFET and SBD into independent paths. By taking out the thermal measurement capability from the integrated structure, each chip type can be measured independently without thermal interference from the other.
2Measurement precision
If MOSFET and SBD chips are mounted on separate die pads, then thermal interference is reduced for accurate measurement, but device structure becomes more complex
Solution Approach 1:
The patent applies universality by using identical die pad structures for both MOSFET and SBD mounting. Each die pad follows the same design pattern with corresponding terminals, making the overall device structure systematic and manageable despite having separate mounting regions. This multi-functional approach allows the same structural template to serve both chip types.
Solution Approach 2:
The patent employs nesting by placing multiple terminal structures within the overall device housing in a organized manner. The separate die pads and their associated terminals are nested within the common device structure, creating a hierarchical organization that manages complexity through structured arrangement.
Data Source
AI summary
An object of the present disclosure is to facilitate thermal design in a semiconductor device in which MOSFETs and SBDs are connected in antiparallel. The semiconductor device includes a MOSFET chip provided on a first pattern, whose drain electrode and source electrode are electrically connected to the first pattern and a second pattern, respectively, an SBD chip provided on a third pattern, whose cathode electrode and anode electrode are electrically connected to the third pattern and fourth pattern, respectively, a drain main terminal connected to the first pattern, a source main terminal connected to the second pattern, a cathode main terminal connected to the third pattern, and an anode main terminal connected to the fourth pattern. At least one of between the drain main terminal and the cathode main terminal and between the source main terminal and the anode main terminal is not electrically connected.