MOSFET Gate Stack with Scandium Capping Layer
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Solution Overview
Problem
The introduction of high-k dielectrics in MOSFET transistors leads to Fermi level pinning issues due to interfacial bonds, causing high threshold voltages and complexity in manufacturing, particularly with polysilicon gates, where finding compatible band-edge metals is challenging and FUSI gates suffer from threshold voltage non-uniformity on small devices.
Innovation Solution
A semiconductor device with a Sc-based dielectric capping layer over high-k dielectric layers, allowing for polysilicon gates with controlled doping, reducing Fermi level pinning and maintaining compatibility with CMOS processes by using Sc-oxide or Sc-silicate capping layers, which do not significantly alter the work function and reduce equivalent oxide thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high-k dielectric layers are introduced to reduce gate leakage, then gate leakage current is reduced, but Fermi level pinning occurs causing high threshold voltages
Solution Approach 1:
A Sc-based dielectric capping layer is introduced as an intermediary between the high-k dielectric layer and the polysilicon gate electrode. This intermediate layer prevents direct contact between the high-k dielectric and polysilicon, thereby eliminating Fermi level pinning while preserving the low gate leakage benefits of the high-k dielectric. The Sc-based layer acts as a buffer that mediates the interaction between the two materials.
Solution Approach 2:
The gate stack is constructed as a composite structure comprising multiple layers: high-k dielectric layer, Sc-based dielectric capping layer, and polysilicon gate electrode. This composite material approach combines the advantages of different materials - the high-k dielectric for low leakage, the Sc-based capping layer for Fermi level control, and polysilicon for gate functionality - to achieve overall performance improvement.
2Reliability
If metal gates are used to overcome Fermi level pinning, then threshold voltage control is improved, but manufacturing complexity and costs increase
Solution Approach 1:
The invention uses polysilicon gate electrode instead of expensive metal gates, sacrificing some of the ideal threshold voltage control that metal gates could provide, but gaining significant advantages in manufacturing simplicity and cost. The Sc-based capping layer compensates for the limitations of polysilicon, making this a cost-effective solution.
Solution Approach 2:
The Sc-based dielectric capping layer modifies the electrical parameters at the gate interface by preventing Fermi level pinning, thereby changing the work function characteristics and threshold voltage behavior of the polysilicon gate to achieve performance comparable to metal gates without the associated complexity.
3Device complexity
If FUSI gates are used to avoid selective removal, then manufacturing complexity is reduced, but within-wafer threshold voltage non-uniformity increases
Solution Approach 1:
The Sc-based dielectric capping layer is deposited uniformly across the entire wafer surface, providing consistent Fermi level pinning prevention across all devices. This homogeneous application ensures uniform threshold voltage characteristics across the wafer, overcoming the non-uniformity issues associated with FUSI gates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces Fermi level pinning, maintains performance, and simplifies the manufacturing process by using polysilicon gates with Sc-based capping layers, achieving uniform threshold voltages and cost-effectiveness compared to metal gated devices.
Implementation Method 1
Fermi level pinning. The Fermi level pinning effect takes place at the polysilicon (poly-Si)/metal oxide interface and causes high threshold voltages in MOSFET devices.
Data Source
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AI summary
A semiconductor device is disclosed. The device comprises a first MOSFET transistor. The transistor comprises a substrate, a first high-k dielectric layer upon the substrate, a first dielectric capping layer upon the first high-k dielectric, and a first gate electrode made of a semiconductor material of a first doping level and a first conductivity type upon the first dielectric capping layer. The first dielectric capping layer comprises Scandium.