MOSFET Structure With Vertical Screening Layer for Low Leakage
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Solution Overview
Problem
Current planar MOSFETs face challenges such as short channel effects, increased leakage currents, and difficulty in controlling effective channel length due to dopant diffusion and non-uniform doping, leading to issues like punch-through and gate-induced drain leakage, especially at mature technology nodes like 12-30 nm.
Innovation Solution
A novel MOSFET structure is introduced, featuring a vertical screening layer with a different doping type than the conductive region, independent from the semiconductor substrate, and a P-N junction aligned with the gate edge, along with a shallow trench isolation and selective epitaxy growth to form crystalline silicon regions, reducing leakage and enhancing channel control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion-implantation plus thermal annealing technique is used to form source and drain regions, then dopants are implanted into substrate, but dopants diffuse into different directions and enlarge source and drain regions, reducing effective channel length and causing short channel effect
Solution Approach 1:
The source and drain regions are segmented into multiple zones with different doping concentrations: lightly-doped drain (LDD) regions adjacent to the channel, and heavily-doped source/drain regions further from the channel. This segmentation prevents uniform dopant diffusion from enlarging the entire source/drain structure, thereby preserving the effective channel length while still providing necessary electrical functionality.
Solution Approach 2:
Different regions of the source and drain structures are given different doping qualities: the LDD regions have lower doping concentrations to minimize diffusion and preserve channel length, while the heavily-doped regions provide strong electrical contact. This local differentiation resolves the contradiction by optimizing each region's doping characteristics for its specific function.
2Reliability
If reserved longer gate length is used to accommodate dopant diffusion, then short channel effect is reduced, but transistor size cannot be proportionally shrunk
Solution Approach 1:
The source/drain structure is segmented into LDD and heavily-doped regions, allowing the gate length to be scaled down without the entire source/drain structure expanding. The LDD region acts as a buffer that accommodates limited diffusion while the heavily-doped region maintains electrical functionality, enabling continued transistor scaling while controlling SCE.
Solution Approach 2:
The doping concentration parameter is changed across different regions: low concentration in LDD regions to minimize diffusion, high concentration in heavily-doped regions for electrical performance. This parameter variation allows shorter gate lengths to be used without proportionally increasing source/drain dimensions, thus enabling transistor scaling while maintaining SCE control.
3Quantity of substance
If ion-implantation is used to form LDD and source/drain regions, then dopants are inserted into substrate, but non-uniform dopant distribution is created with higher concentrations at top surface, making uniform material interfaces difficult
Solution Approach 1:
The dopant distribution is segmented into distinct concentration zones: the LDD regions receive lower doping concentrations while the heavily-doped source/drain regions receive higher concentrations. This segmentation creates a controlled non-uniform distribution that is intentional and functional, rather than a defect, allowing uniform interfaces at critical boundaries while maintaining necessary dopant quantities.
Solution Approach 2:
Different local regions are given different dopant qualities: LDD regions have low doping for uniform interfaces and minimal diffusion, while heavily-doped regions have high doping for electrical performance. This local quality differentiation resolves the contradiction by making non-uniform distribution a deliberate design feature rather than a manufacturing defect.
4Reliability
If thermal annealing process is used to remove ion-implantation damages, then lattice defects are reduced, but gate-induced drain leakage current is induced due to gated diode structure
Solution Approach 1:
The source/drain structure is segmented into LDD and heavily-doped regions, which modifies the electric field distribution during thermal annealing. The LDD region acts as a field buffer that reduces the formation of strong gated diode structures, thereby minimizing GIDL current while still allowing thermal annealing to effectively remove lattice defects from the heavily-doped regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes leakage currents, improves channel conduction performance, and maintains precise control over source and drain regions, reducing the short channel effect and punch-through probability while eliminating the need for thermal annealing, thereby enhancing transistor efficiency and reliability.
Implementation Method 1
A novel MOSFET structure with a vertical screening layer... capable to block leakage current and to reduce the possibility of punch through effect... The P-N junction extends upward from the isolation region and along an edge of the first conductive region
Implementation Method 2
selective epitaxy growth to form crystalline silicon regions
Data Source
AI summary
A metal-oxide-semiconductor field-effect transistor (MOSFET) structure includes a semiconductor substrate, a gate structure, a channel region, a channel region, a trench, an isolation region, a first conductive region, and a P-N junction. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface. The channel region is under the gate structure. The trench is formed below the semiconductor surface and adjacent to the channel region. The isolation region is in the trench. The first conductive region has a first doping type, and the first conductive region is positioned on the isolating layer and electrically coupled to the channel region. The P-N junction extends upward from the isolation region and along an edge of the first conductive region.