MOSFET Segment Layout for ESD Protection

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Solution Overview

Problem

Existing integrated circuit (IC) ESD protection networks face challenges in maximizing the number of MOSFET segments that enter the snapback regime during an ESD event, leading to potential physical damage to the first segment that initiates snapback, and adding complexity with feedback paths or reducing available transistor fingers for current sinking.

Innovation Solution

The proposed solution involves a layout where well-ties are connected to a fixed voltage reference, allowing current to flow more readily from a segment experiencing snapback to adjacent segments through well-tie structures, facilitating snapback in adjacent segments and reducing non-uniform current conduction, thereby enhancing protection without additional complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If MOSFET segments are separated by well-ties to improve latch-up robustness, then reliability is improved, but current flow between segments is blocked during snapback events

Engineering Contradiction:
Improvelatch-up robustnessVSAvoidnon-uniform current conduction
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A shared source/drain region is introduced as an intermediary conductive path between MOSFET segments. This shared region allows snapback current to flow laterally from one segment to adjacent segments through the source/drain region, which acts as a mediator that connects segments electrically while maintaining their physical separation by well-ties. The shared source/drain region thus enables current redistribution without compromising the latch-up protection provided by well-ties.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If the first MOSFET segment to enter snapback sinks all ESD current, then ESD protection is provided, but the first segment suffers physical damage

Engineering Contradiction:
ImproveESD protectionVSAvoidsegment durability
Core Design Contradiction:
Object-affected harmful factorsVSStrength

Solution Approach 1:

The shared source/drain region creates a feedback mechanism where the voltage drop and current flow in one MOSFET segment during snapback automatically influence adjacent segments. As the first segment enters snapback and experiences voltage changes, these changes are fed back through the shared source/drain region, triggering snapback in adjacent segments. This feedback loop ensures progressive activation of multiple segments, distributing the ESD current load and preventing any single segment from bearing the full burden.

Inventive Principle:
Principle #23Feedback

3Reliability

If feedback paths are added to facilitate snapback in adjacent segments, then current distribution is improved, but circuit complexity increases

Engineering Contradiction:
Improvecurrent distribution uniformityVSAvoidcircuitry complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The shared source/drain region provides self-service functionality by automatically enabling current redistribution during snapback events without requiring external control circuits or additional feedback components. The physical coupling through the shared source/drain region inherently creates the necessary feedback path, allowing the device to self-regulate current distribution among segments based on their individual snapback characteristics. This eliminates the need for complex external feedback circuitry while achieving uniform current conduction.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This layout design increases the reliability of the ESD protection by ensuring more segments enter the snapback regime, reducing the likelihood of physical damage to the initial segment and maintaining latch-up robustness while simplifying the circuitry.

Implementation Method 1

current to flow more readily from a segment experiencing snapback to adjacent segments through well-tie structures

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

one of the transistor segments can experience snapback before another segment... facilitating snapback in adjacent segments

Methodology Applied
Scientific EffectSnapback: Avalanche Breakdown

Data Source

PatentUS9202808B2Integrated circuit electrical protection device
Publication Date: 2015.12.01 NXP USA INC
  • US9202808B2 patent drawing
  • US9202808B2 patent drawing
  • US9202808B2 patent drawing

AI summary

An integrated circuit electrical protection device is disclosed that includes a semiconductor substrate and a plurality of transistor fingers partitioned into a plurality of segments. The segments are distinguished from one another by well-ties spaced apart from each other within a source/drain region that is shared by adjacent segments.