Trench Gate MOSFET with Segmented Base-Bottom Buried Region
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Solution Overview
Problem
In trench gate MOSFETs using wide band gap semiconductors like silicon carbide, the high voltage applied to the gate insulating film at the bottom of the trench poses a risk of breakdown, and existing structures that attempt to relax the electric field can lead to decreased breakdown voltage and increased avalanche current flow at the bottom of the trench.
Innovation Solution
The implementation of a semiconductor device structure that includes a drift layer, a current spreading layer with higher impurity concentration, a base region, a main electrode region, a gate-bottom protection region, and base-bottom buried regions with specific impurity concentrations and configurations to prevent avalanche current flow at the trench bottom while maintaining breakdown voltage, including a separation layer to divide the base-bottom buried regions in the depth direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p+-type region is provided at the bottom of the trench and a p+-type region is provided below a contact region to relax the electric field intensity, then the electric field intensity at the bottom of the trench is relaxed, but the breakdown voltage of the active area is decreased and avalanche current flows more easily
Solution Approach 1:
The base-bottom buried region is divided into multiple regions by separation layers, creating a segmented structure that prevents concentrated avalanche current flow while distributing the electric field relaxation function across multiple zones
Solution Approach 2:
Different regions are assigned different impurity concentrations and structural characteristics - the gate-bottom protection region has high impurity concentration for electric field relaxation, while the base-bottom buried region has lower impurity concentration and is segmented to prevent avalanche current, creating local quality differences that resolve the contradiction
2Ease of operation
If an n+-type region is selectively formed under the p+-type region below the contact region to concentrate the electric field, then avalanche current can flow more easily, but the breakdown voltage of the active area and peripheral area are decreased
Solution Approach 1:
The problematic n+-type region that concentrates electric field and reduces breakdown voltage is removed entirely. Instead, a base-bottom buried region with lower impurity concentration is provided, which relaxes the electric field without creating localized high-field regions that would reduce breakdown voltage
Solution Approach 2:
The solution moves from vertical electric field concentration (n+-type region under p+-type region) to horizontal electric field relaxation through the base-bottom buried region extending in the planar direction, changing the dimension of electric field management
Data Source
AI summary
An insulated-gate semiconductor device includes: an n-type current spreading layer provided on an n−-type drift layer; a p+-type base region provided on the current spreading layer; an n+-type source region provided in an upper portion of the base region; an insulated-gate electrode structure provided inside a trench; a p+-type gate-bottom protection-region provided in the current spreading layer so as to be in contact with a bottom of the trench; and a p+-type base-bottom buried-region buried in the current spreading layer, having a bottom surface having the same depth as a bottom surface of the gate-bottom protection-region, wherein the base-bottom buried-region is divided into a plurality of portions in a depth direction through an n-type separation layer.