MOSFET Source/Drain Dimension Control via Self-Aligned Spacers
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Solution Overview
Problem
The challenge is to shrink the size of metal-oxide-semiconductor field-effect transistors (MOSFETs) to integrate more transistors on a silicon wafer while minimizing leakage currents and power consumption, which is hindered by misalignment tolerances in photolithographic equipment, making it difficult to reduce the size of source and drain areas and contact holes.
Innovation Solution
A transistor structure and manufacturing method that precisely control the lengths of source/drain and contact openings using a single photolithography process, eliminating misalignment tolerances by forming self-alignment pillars and spacers to define the dimensions of the gate, source, drain, and contact holes, allowing for features as small as the minimum feature size without additional misalignment tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithographic masking technology is used to define source/drain and contact hole dimensions, then manufacturing process is simplified, but misalignment tolerance (Δλ) prevents further miniaturization below λ + Δλ
Solution Approach 1:
The patent introduces self-aligned spacer structures as intermediary elements between the photolithographically defined gate and the source/drain regions. These spacers act as mediators that automatically define the precise position and dimension of contact holes and source/drain areas through conformal deposition and etching, eliminating the need for separate photolithography alignment steps. The spacer thickness, controlled by atomic layer deposition (ALD), serves as the critical dimension control mechanism, achieving precision far below the photolithography limit of λ + Δλ.
Solution Approach 2:
The self-aligned spacer structures perform multiple functions automatically: they define the contact hole position, define the source/drain region boundary, and control the critical dimensions without requiring additional alignment steps. The process uses the gate structure itself as the reference for spacer formation, and the spacers subsequently serve as masks for defining the contact holes and source/drain regions, making the system self-defining and self-aligning throughout the fabrication sequence.
2Productivity
If transistor dimensions are shrunk to increase integration density, then more transistors fit on silicon wafer, but misalignment tolerance prevents source/drain length from being smaller than λ + Δλ
Solution Approach 1:
Self-aligned spacers are introduced as intermediary structures that decouple the photolithography resolution limit from the actual source/drain dimension control. The spacers are formed by conformal deposition around the gate and are subsequently used to define the source/drain regions through etching. This intermediary approach allows the source/drain length to be precisely controlled by the spacer thickness (via ALD) rather than being limited by photolithography alignment tolerance, enabling dimensions smaller than λ + Δλ while maintaining high integration density.
Solution Approach 2:
The patent changes the critical dimension control parameter from photolithography wavelength (λ) and alignment tolerance (Δλ) to atomic layer deposition film thickness. By using ALD to deposit the spacer material, the critical dimension control shifts to a thin-film deposition process that can achieve sub-nanometer precision, fundamentally changing the limiting factor from optical resolution to atomic-layer film thickness control, thereby enabling much smaller source/drain dimensions.
3Area of stationary object
If contact hole size is reduced to shrink transistor area, then integration density increases, but photolithography misalignment makes contact hole positioning within drain difficult below λ dimension
Solution Approach 1:
The self-aligned spacer structures serve as intermediaries that automatically position contact holes with precision far below the photolithography limit. The spacers are formed conformally on the gate and isolation structures, and their outer edges automatically define the contact hole positions through subsequent etching. This eliminates the need for separate contact hole photolithography alignment steps, achieving positioning accuracy determined by spacer thickness control (via ALD) rather than photolithography alignment tolerance, enabling contact holes smaller than λ to be precisely positioned within the source/drain regions.
Solution Approach 2:
The spacer structures perform the dual function of defining both the source/drain region boundaries and the contact hole positions in a self-aligned manner. The same spacer that defines the source/drain extent also serves as the mask for contact hole formation, automatically ensuring precise positioning without requiring additional photolithography steps. This self-service approach eliminates misalignment issues entirely, as the contact hole position is inherently tied to the source/drain region definition.
Data Source
Figure 1
Figure 2A
Figure 2B~2C
AI summary
A transistor structure includes a semiconductor substrate, a gate structure (101), a channel region, a first conductive region, and a contact hole (109, 111). The semiconductor substrate has a semiconductor surface. The gate structure has a length (G(L)). The first conductive region is electrically coupled to the channel region. The contact hole is positioned above the first conductive region. A periphery of the contact hole is surrounded by a circumference of the first conductive region.