MOSFET Shallow Trench Termination for Dielectric Lifetime
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Solution Overview
Problem
Semiconductor devices with reduced oxide layer lifetime due to overlap between gate dielectric and trench corners, leading to time-dependent dielectric breakdown (TDDB), and increased footprint to maintain performance, limiting their applicability.
Innovation Solution
Terminating shallow trenches before the channel region to prevent dielectric overlap with trench corners, using a dielectric layer that does not cover the substrate boundaries, and incorporating a void to separate gate dielectrics, allowing for improved electric field distribution and reduced hot carrier injection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If shallow trenches are extended through the channel region into the source region to avoid dielectric overlap with trench corners, then device footprint is reduced, but current drive decreases
Solution Approach 1:
The invention segments the trench structure into two distinct types: shallow trenches filled with insulating material that terminate before the channel region, and deeper isolation trenches that extend through the channel region. This segmentation allows the shallow trenches to reduce footprint while the deeper isolation trenches maintain current drive by preventing dielectric overlap with trench corners in the active channel area.
Solution Approach 2:
The invention introduces an intermediary structure - the deeper isolation trench - that mediates between the footprint-reducing shallow trenches and the current-drive-maintaining requirement. The isolation trench acts as a buffer that prevents the harmful dielectric overlap effect while allowing the shallow trenches to extend further for compactness.
2Reliability
If dielectric layer covers trench corners to provide continuous insulation, then electrical isolation is improved, but gate dielectric lifetime decreases due to thinning over trench corners
Solution Approach 1:
The invention extracts the dielectric layer from covering the trench corners by terminating the shallow trenches before the channel region. This removes the source of the problem (dielectric thinning over trench corners) while maintaining electrical isolation through the deeper isolation trenches that extend through the channel region.
Solution Approach 2:
The invention addresses the two-dimensional problem of dielectric coverage by introducing a vertical dimension - deeper isolation trenches that extend through the channel region. This vertical extension provides the necessary electrical isolation without requiring the problematic horizontal extension of shallow trenches under the gate dielectric.
3Reliability
If additional mask and processing steps are added to achieve better breakdown voltage performance, then device performance is improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The invention merges the formation of shallow trenches and isolation trenches into a single etching process using a common mask pattern. This combines what would traditionally require separate processing steps into one unified operation, achieving both footprint reduction and electrical isolation without increasing manufacturing complexity.
Solution Approach 2:
The single mask pattern used to define the shallow trenches also serves to define the isolation trenches, making the process universal and eliminating the need for additional mask steps. The same etching process creates both trench types, achieving multi-functionality in a single operation.
Data Source
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AI summary
A semiconductor device eg. a MOSFET (1) comprising a substrate (40) including a first region (18) and a second region (16) of a first conductivity type and a third region (42) between the first and second regions of a type opposite to the first conductivity type, and being covered by a dielectric layer (20), a plurality of trenches (12) laterally extending between the third and second region, said trenches being filled with an insulating material, and being separated by active stripes (14) comprising a doping profile having a depth not exceeding the depth of the trenches wherein each trench terminates before reaching the dielectric layer (20),namely is separated from the third region by a substrate portion (26) such that the respective boundaries between the substrate portions and the trenches are not covered by the dielectric layer. A method for manufacturing such a semiconductor device is also disclosed.