MOSFET Current-Sensing Layout With Shared Isolation Wells
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Solution Overview
Problem
The challenge of reducing the die size of integrated circuits utilizing transistors as current sensing elements is exacerbated by the need to isolate each transistor to avoid short circuits, which occupies significant physical space on the die.
Innovation Solution
Implementing a semiconductor design that combines a series of MOSFETs with Ndrift resistors, which do not include a positively doped body region, allowing them to be placed in a single isolation tank/well, reducing the need for separate wells and minimizing die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are isolated in separate wells to avoid short circuits, then reliability is improved, but die area increases
Solution Approach 1:
Multiple transistors that would traditionally require separate isolation wells are merged into a single shared isolation well. The patent places several transistor structures (including sensing transistors and power transistors) within one common well region, eliminating the need for individual wells around each transistor. This merging approach maintains electrical isolation where needed while significantly reducing the total die area consumed by isolation structures.
2Reliability
If separate isolation wells are used for each transistor, then device reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple isolation functions into a single shared isolation well structure. Instead of creating separate isolation regions for each transistor, the design uses one common isolation well that serves multiple transistors simultaneously. This reduces the number of isolation structures from many individual wells to a smaller number of shared wells, simplifying the overall device architecture and reducing manufacturing complexity.
3Productivity
If transistors are placed closer together to reduce die size, then productivity is improved, but risk of short circuits increases
Solution Approach 1:
The patent merges multiple transistors into shared isolation wells, allowing them to be placed closer together on the die while maintaining proper electrical isolation. This approach enables higher transistor density and smaller die size without increasing short circuit risk, because the shared isolation structures provide adequate separation between adjacent transistor regions.
Solution Approach 2:
The patent applies isolation structures selectively at specific locations where electrical separation is needed, rather than surrounding every transistor individually. By placing isolation wells only at critical interfaces between different transistor types or functions, the design achieves adequate protection against short circuits while minimizing the total isolation area and maximizing transistor density.
Data Source
AI summary
An example apparatus includes a metal-oxide-semiconductor (MOS), a first negative well, a second negative well, wherein the MOS is between the first negative well and the second negative well, a third negative well; and at least four negatively doped drift (Ndrift) regions, wherein the four Ndrift regions are between the second negative well and the third negative well.