MOSFET Source/Drain Sidewall Structure for Scaled-Down Reliability
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Solution Overview
Problem
The scaling down of MOSFETs in semiconductor devices leads to deterioration in operation characteristics, necessitating improvements in electrical and reliability characteristics.
Innovation Solution
A semiconductor device design featuring specific source/drain patterns with varying semiconductor layers and gate spacers, including convex-shaped inner sidewalls and distinct sidewall distances, along with a method of fabrication involving selective epitaxial growth and controlled process conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If MOSFETs are scaled down to meet increasing demand for smaller pattern sizes, then device size is reduced, but operation characteristics deteriorate
Solution Approach 1:
The patent applies local quality by creating non-uniform width in the first semiconductor layer through selective epitaxial growth. The inner sidewalls are positioned closer to the gate spacer in regions adjacent to the gate spacer, while maintaining larger width in other regions. This local variation in dimensions optimizes electrical characteristics specifically in critical areas without requiring overall device scaling, thus maintaining operation characteristics while achieving compact design.
Solution Approach 2:
The patent transitions from conventional two-dimensional planar structures to three-dimensional structures by forming multi-layer semiconductor stacks with varying widths at different heights. The first semiconductor layer has a non-uniform cross-sectional shape with different widths at different vertical positions, creating a three-dimensional configuration that improves electrical characteristics without increasing the device footprint.
2Ease of manufacture
If conventional uniform semiconductor layers are used in scaled-down devices, then manufacturing is simpler, but electrical performance deteriorates
Solution Approach 1:
The patent changes the geometric parameters of the semiconductor layer by forming a first semiconductor layer with non-uniform width through selective epitaxial growth. The width of the first semiconductor layer varies along the longitudinal direction, being smaller in regions adjacent to the gate spacer and larger in other regions. This parameter variation is achieved through controlled epitaxial growth conditions, maintaining manufacturing feasibility while significantly improving electrical performance.
Solution Approach 2:
The patent performs preliminary action by forming the gate spacer structure before completing the semiconductor layer formation. The selective epitaxial growth of the first semiconductor layer is conducted in the presence of the gate spacer, allowing the layer to conformally grow with varying width based on the spacer's position. This preliminary placement of the gate spacer enables subsequent selective growth that optimizes electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances electrical performance and reliability by optimizing the source/drain patterns and gate spacers, addressing the challenges of scale-down while maintaining high performance.
Implementation Method 1
forming a first semiconductor layer on the sacrificial layers and the semiconductor patterns exposed by the recess and forming a second semiconductor layer on the first semiconductor layer
Data Source
AI summary
A semiconductor device includes a substrate including an active pattern; a source/drain pattern on the active pattern; a gate electrode on the active pattern; and a gate spacer on the source/drain pattern. The source/drain pattern includes a first semiconductor layer on the active pattern and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes a first inner sidewall and second inner sidewall on the second semiconductor layer. A distance between the first and second inner sidewalls of the first semiconductor layer decreases according as positions of two portions of the first semiconductor layer where the distance is measured become closer to the gate spacer decreases.