MOSFET Drain Silicide Blocking Structure for Lower GIDL

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Field-effect transistors (FETs), particularly metal-oxide-semiconductor field-effect transistors (MOSFETs), face challenges with off-state leakage current due to gate-induced drain leakage (GIDL), which results in high standby power consumption.

Innovation Solution

The implementation of a semiconductor device design where the source/drain regions are spaced from the gate electrode by a sidewall spacer and a silicide blocking structure, reducing the formation of deep-depletion regions and thus minimizing GIDL.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If source/drain regions are positioned close to the gate electrode to improve device compactness, then device area is reduced, but gate-induced drain leakage increases causing high standby power consumption

Engineering Contradiction:
Improvedevice areaVSAvoidstandby power consumption
Core Design Contradiction:
Area of stationary objectVSLoss of energy

Solution Approach 1:

A silicide blocking structure is introduced as an intermediary element positioned between the gate electrode and the source/drain regions. This silicide blocking structure acts as a mediator that prevents direct interaction between the gate and source/drain, thereby blocking the leakage current path while allowing the device to maintain compact dimensions. The silicide blocking structure is formed of silicide material that is deposited or grown in the region between the gate and source/drain, creating a physical and electrical barrier that reduces GIDL without requiring increased spacing between components.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of energy

If source/drain regions are spaced further from the gate electrode to reduce GIDL, then standby power consumption is reduced, but device area increases

Engineering Contradiction:
Improvestandby power consumptionVSAvoiddevice area
Core Design Contradiction:
Loss of energyVSArea of stationary object

Solution Approach 1:

The silicide blocking structure extends in the vertical dimension above the source/drain regions and sidewall spacers, rather than requiring increased lateral spacing. By utilizing the vertical space above existing structures, the blocking structure achieves effective GIDL reduction without increasing the device footprint. The silicide blocking structure is positioned at a height that allows it to overlap with the gate electrode vertically, creating a blocking effect in the vertical dimension while maintaining compact lateral dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Loss of energy

If a silicide blocking structure is added to reduce GIDL, then standby power consumption is reduced, but device complexity increases

Engineering Contradiction:
Improvestandby power consumptionVSAvoiddevice complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The formation of the silicide blocking structure is merged with existing fabrication processes, particularly the silicidation steps used to form source/drain contacts and other silicide structures in the device. The same silicide deposition and annealing processes that create other silicide features in the device are used to form the blocking structure, eliminating the need for separate process steps. The silicide blocking structure is formed concurrently with other silicide features through unified process integration, reducing overall device complexity despite the additional functional element.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250120153A1Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices
Publication Date: 2025.04.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250120153A1 patent drawing
  • US20250120153A1 patent drawing
  • US20250120153A1 patent drawing

AI summary

In some embodiments, an integrated chip is provided. The integrated chip includes a source region and a drain region disposed in a substrate. A gate is disposed over the substrate and between the source region and the drain region. A silicide structure is disposed over the drain region. A first silicide blocking segment and a second silicide blocking segment are disposed directly over the drain region. The silicide structure continuously extends over the drain region from a first sidewall contacting the first silicide blocking segment to a second sidewall contacting the second silicide blocking segment, in a cross-sectional view.