MOSFET Silicide Thickness Layout for PMOS Hole Mobility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of metal oxide semiconductor field effect transistors (MOSFETs) deteriorate, necessitating improved methods for fabricating devices with superior performance while addressing high integration issues.
Innovation Solution
The semiconductor device includes distinct active regions with varying silicide patterns, where the silicide pattern on the PMOSFET region is thicker and larger in volume than that on the NMOSFET region, providing compressive stress to enhance hole mobility and improve operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to achieve higher integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent applies different silicide pattern thicknesses to different transistor types within the same integrated circuit. Specifically, PMOSFET regions receive thicker silicide patterns while NMOSFET regions receive thinner silicide patterns. This local differentiation allows each transistor type to be optimized independently for its specific electrical characteristics, thereby maintaining high operating performance despite overall device scaling and high integration density.
2Ease of manufacture
If uniform silicide patterns are used across all active regions, then manufacturing simplicity is maintained, but hole mobility in PMOSFETs cannot be enhanced
Solution Approach 1:
The patent implements non-uniform silicide patterns where the thickness varies by active region type. PMOSFET active regions are equipped with thicker silicide patterns to provide enhanced compressive stress that improves hole mobility, while NMOSFET regions use thinner silicide patterns. This localized quality adjustment resolves the contradiction by prioritizing electrical performance where needed while maintaining overall manufacturing feasibility through a systematic fabrication process.
Solution Approach 2:
The patent changes the physical parameter of silicide pattern thickness based on the specific active region requirements. By adjusting the thickness parameter differently for PMOSFET and NMOSFET regions, the patent optimizes the electrical properties of each transistor type. The thicker silicide in PMOSFET regions specifically targets hole mobility enhancement through stress engineering, demonstrating parameter change as a solution to the contradiction between manufacturing simplicity and performance optimization.
3Reliability
If thicker silicide patterns are applied to all regions, then hole mobility improves, but manufacturing complexity and material usage increase
Solution Approach 1:
The patent applies thicker silicide patterns selectively only to PMOSFET active regions where hole mobility enhancement is needed, rather than uniformly to all regions. This localized application achieves the desired electrical performance improvement while minimizing the increase in manufacturing complexity. The fabrication process uses region-specific processing steps that target PMOSFET areas, thereby avoiding unnecessary material usage and process complexity in NMOSFET regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases electrical properties by enhancing hole mobility and operating speed of PMOSFETs, thereby improving the overall performance of the semiconductor device.
Implementation Method 1
the silicide pattern on the PMOSFET region is thicker and larger in volume than that on the NMOSFET region, providing compressive stress to enhance hole mobility
Data Source
AI summary
A semiconductor device may include first and second active regions on a substrate, first and second active patterns on the first and second active regions, first and second source/drain patterns on the first and second active patterns, first and second silicide patterns on the first and second source/drain patterns, and first and second active contacts coupled to the first and second source/drain patterns. A lowermost portion of the first active contact is at a level higher than that of a lowermost portion of the second active contact. A thickness of the first silicide pattern is greater than that of the second silicide pattern.