MOSFET Source Side Implantation After Spacer Formation
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Solution Overview
Problem
The reduction in size of metal oxide semiconductor field effect transistor (MOSFET) gate length is limited by short channel effects, such as punch-through and drain-induced barrier lowering, leading to increased leakage currents and reduced breakdown voltage due to the short effective channel length between the source and drain regions.
Innovation Solution
The MOSFET structure is enhanced by forming source and drain regions aligned with sidewall spacers to extend the effective channel length, reducing short channel effects and increasing breakdown voltage by separating the depletion regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the gate length of MOSFET is reduced to shrink memory cell size, then the memory capacity increases, but short channel effects such as punch-through and drain-induced barrier lowering increase, leading to higher leakage currents
Solution Approach 1:
The patent introduces offset regions that extend laterally beyond the gate edges in the horizontal dimension, effectively increasing the channel length without increasing the vertical device footprint. This dimensional approach allows continued memory scaling while maintaining adequate channel control and reducing short channel effects.
Solution Approach 2:
The channel region is segmented into distinct portions: the main channel under the gate and the offset regions extending beyond the gate edges. This segmentation allows independent optimization of each region, with offset regions providing additional channel length and control over depletion region interactions.
2Speed
If the effective channel length is reduced to increase transistor speed, then the switching speed improves, but the depletion regions from source and drain overlap, causing punch-through and loss of gate control
Solution Approach 1:
Offset regions are formed that extend laterally beyond the gate edges, adding channel length in the horizontal dimension without increasing the vertical device area. This maintains fast switching characteristics while preventing depletion region overlap and preserving gate control.
Solution Approach 2:
Offset regions are formed prior to source and drain region formation, establishing predetermined spacing between source and drain regions before doping occurs. This preliminary structural arrangement ensures adequate channel length is maintained before the depletion regions are created during subsequent processing steps.
3Area of stationary object
If source and drain regions are formed with standard alignment to maximize memory density, then the cell area is minimized, but the effective channel length becomes too short, reducing breakdown voltage
Solution Approach 1:
Offset regions extend the channel laterally beyond the gate edges, increasing the effective channel length and thus the breakdown voltage without increasing the vertical device footprint. This maintains high memory density while improving electrical breakdown characteristics.
Data Source
AI summary
The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.