Low Voltage MOSFET with Source Trench and P+ Plug
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Solution Overview
Problem
There is a need for semiconductor devices, particularly MOSFETs, that can operate at low voltage levels suitable for portable electronic devices and data processing centers, as existing power supplies often require conversion of AC or high voltage DC to lower voltage DC, which is not efficiently managed by conventional MOSFETs.
Innovation Solution
The method involves forming a semiconductor device with a substrate, well region, gate structure, source and drain regions, trench, plug, and interconnect structure, specifically designing a low voltage MOSFET cell with a source trench, P+ plug, and co-implanted clamp diodes to reduce resistance and enhance robustness, allowing for efficient low voltage operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional MOSFETs are used for power supply conversion, then high voltage DC to low voltage DC conversion is achieved, but power efficiency and performance are insufficient for portable electronic devices and data processing centers
Solution Approach 1:
The patent changes the electrical parameters of the MOSFET by introducing a P+ plug region with high doping concentration (1E19 to 1E21 atoms/cm³) into the N- drift region. This parameter change reduces the drain-source resistance (RDS(on)) and improves power efficiency while maintaining voltage blocking capability, resolving the contradiction between power efficiency and performance robustness
Solution Approach 2:
The patent applies local quality by creating a P+ plug region at a specific location within the N- drift region, rather than uniformly modifying the entire structure. This localized modification reduces resistance in the critical current path while preserving the voltage blocking properties of the drift region, enabling improved power efficiency without sacrificing performance robustness
2Use of energy by moving object
If MOSFETs are designed for low voltage operation, then power consumption is reduced, but robustness and reliability are compromised
Solution Approach 1:
The patent changes the doping concentration parameter by introducing heavily doped P+ regions (1E19 to 1E21 atoms/cm³) into the lightly doped N- drift region (1E15 to 1E18 atoms/cm³). This creates a resistance reduction effect that lowers power consumption while the P+ regions also provide clamping action that protects against voltage spikes, thereby maintaining device robustness
Solution Approach 2:
The P+ plug acts as an intermediary element between the source and drain regions. It provides a low-resistance path for current flow (reducing power consumption) while also serving as a clamping mechanism that limits voltage stress on other device components (maintaining robustness). This intermediary structure resolves the contradiction between low power consumption and high reliability
3Use of energy by moving object
If drain-source resistance is reduced for better low voltage performance, then power efficiency improves, but device complexity increases
Solution Approach 1:
The patent segments the N- drift region by introducing discrete P+ plug regions within it. This segmentation creates multiple localized low-resistance paths that collectively reduce the overall drain-source resistance, improving power efficiency. The segmented approach is simpler than completely redesigning the MOSFET structure, as it builds upon the conventional MOSFET architecture with targeted modifications
Data Source
AI summary
A semiconductor device has a well region formed within a substrate. A gate structure is formed over a surface of the substrate. A source region is formed within the substrate adjacent to the gate structure. A drain region is formed within the substrate adjacent to the gate structure. A first clamping region and second clamping region below the source region and drain region. A trench is formed through the source region. The trench allows the width of the source region to be reduced to 0.94 to 1.19 micrometers. A plug is formed through the trench. A source tie is formed through the trench over the plug. An interconnect structure is formed over the source region, drain region, and gate structure. The semiconductor device can be used in a power supply to provide a low voltage to electronic equipment such as a portable electronic device and data processing center.