MOSFET Spacer Air Gaps for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Parasitic/overlap capacitances across sidewall spacers and gate oxide dielectric layers in MOSFET devices degrade performance, particularly in RF MOSFETs, slowing switching speed and compromising short-channel performance.
Innovation Solution
Introduce air gaps in sidewall spacers of MOSFETs to reduce the dielectric constant, thereby lowering junction, overlap, and fringing capacitances, using methods like selective etching and deposition of etch stop layers to form trenches and air gaps in the spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If sidewall spacers with high dielectric constant materials are used, then device structure stability is improved, but parasitic capacitance increases and switching speed decreases
Solution Approach 1:
The patent applies local quality by creating air gaps in specific regions of the sidewall spacers rather than uniformly modifying the entire spacer structure. The air gaps are positioned in the lower portion of the sidewall spacers, while the upper portions maintain their dielectric material structure to provide mechanical support and electrical isolation. This localized modification reduces parasitic capacitance in critical regions while preserving overall structural stability.
Solution Approach 2:
The patent changes the dielectric parameter of the sidewall spacer by introducing air gaps (dielectric constant ≈ 1) within the spacer structure. This creates a composite structure with effectively lower average dielectric constant, reducing the capacitance between the gate and source/drain regions. The parameter change is achieved through controlled etching that removes portions of the dielectric material to form air-filled voids.
2Reliability
If high-k gate and spacer materials are used, then device performance is improved, but fringing capacitance increases and short-channel performance deteriorates
Solution Approach 1:
The patent applies the extraction principle by removing portions of the dielectric material from the sidewall spacers to create air gaps. This extraction eliminates the harmful fringing capacitance effects in the lower regions of the spacers where the electric field lines would otherwise extend into the source and drain regions. The removed material is replaced with air, which has negligible dielectric constant and thus minimal fringing capacitance.
Solution Approach 2:
The patent creates a porous structure within the sidewall spacers by forming air gaps. This porous configuration allows the spacer to maintain its mechanical integrity and electrical isolation functions while having reduced effective dielectric constant. The air-filled voids within the spacer structure act as low-dielectric regions that suppress fringing field effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of air gaps reduces parasitic and fringing capacitances, enhancing switching speed and improving short-channel performance of MOSFET devices.
Implementation Method 1
Parasitic/overlap capacitances resulting from capacitive effects across sidewall spacers and/or from the gate oxide dielectric layer degrade the performance of metal-oxide semiconductor field effect transistor (MOSFET) devices
Implementation Method 2
Introduce air gaps in sidewall spacers of MOSFETs to reduce the dielectric constant, thereby lowering junction, overlap, and fringing capacitances
Data Source
AI summary
A transistor device and method of making the same are disclosed. The transistor device includes one or more air gaps in one or more sidewall spacers. The one or more air gaps may be located adjacent the gate and/or above the source or drain regions of the device. Various embodiments may include different combinations of air gaps formed in one or both sidewall spacers. Various embodiments may include air gaps formed in one or both sidewall spacers adjacent to the gate and/or above the source or drain regions of the device. The formation of the air gaps may reduce unwanted parasitic and/or fringing capacitance.