MOSFET Spacer Formation Using BPSG for Precise Oxide Thickness
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Solution Overview
Problem
The formation of MOSFETs in semiconductor structures is hindered by the difficulty in controlling the thickness of the oxide spacer layer due to the presence of a remaining top oxide layer, leading to unstable source/drain regions and poor electrical properties.
Innovation Solution
A method involving the formation of a boro-phospho-silicate-glass (BPSG) layer on a second dielectric layer, which acts as a mask for etching the metal and semiconductor layers, allowing for the direct formation of a second spacer layer on the exposed top surface of the second dielectric layer, thereby eliminating the need for additional oxide layers and stabilizing the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a traditional oxide layer is used as a mask for etching, then the etching process can be performed, but the remaining top oxide layer interferes with end point detection and makes thickness control difficult
Solution Approach 1:
The patent introduces a BPSG layer as an intermediary mask layer between the etching process and the oxide spacer layer. This BPSG layer serves as a mediator that enables clear end point detection during etching without interfering with the subsequent oxide spacer formation, thus resolving the contradiction between manufacturing precision and detection difficulty
Solution Approach 2:
The patent changes the material parameter of the mask layer from traditional oxide to BPSG (boro-phospho-silicate glass). This parameter change allows for distinct etch selectivity and improved end point detection capability, enabling precise control of the etching process while maintaining compatibility with subsequent processing steps
2Productivity
If the thickness of the remaining top oxide layer varies, then the etching process can proceed, but the source/drain regions implant positions become unstable
Solution Approach 1:
The BPSG layer acts as an intermediary that decouples the etching process from the oxide spacer thickness, allowing efficient etching while maintaining stable implant positions through reliable end point detection
Solution Approach 2:
The patent implements feedback control through end point detection during the etching process. By detecting when the BPSG layer is completely removed, the system can automatically stop the etching process at the precise moment, ensuring consistent oxide spacer thickness and stable source/drain regions implant positions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables stable end point detection for controlling etching process time, allowing for precise control of the second spacer layer thickness, which results in stable source/drain regions' implant positions and improved electrical properties such as saturation current (Idsat).
Implementation Method 1
the BPSG layer has a different etch selectivity from the first dielectric layer
Implementation Method 2
etching the metal layer and the semiconductor layer using the BPSG layer as a mask
Implementation Method 3
forming a second dielectric layer on a portion of the metal layer
Data Source
AI summary
A method of forming a semiconductor structure includes forming a semiconductor layer and a metal layer on a first dielectric layer on a semiconductor substrate in sequence; forming a second dielectric layer on a portion of the metal layer; forming a BPSG layer on the second dielectric layer; etching the metal layer and the semiconductor layer; forming a first spacer layer on sidewalls of the semiconductor layer, the metal layer, and the second dielectric layer, and a top surface of the BPSG layer; etching the first spacer layer to expose the BPSG layer; removing the BPSG layer to expose a top surface of the second dielectric layer; forming a second spacer layer on a sidewall of the first spacer layer and the top surface of the second dielectric layer; and etching the second spacer layer to expose the top surface of the second dielectric layer.